Re: [PATCH 2/2] clk: mediatek: add audsys support for MT2701

2018-03-20 Thread Stephen Boyd 
Quoting Ryder Lee (2018-03-19 20:16:52)
> Add clock driver support for MT2701 audsys.
> 
> Signed-off-by: Ryder Lee 
> ---

Applied to clk-next

Re: [PATCH 2/2] clk: mediatek: add audsys support for MT2701

2018-03-20 Thread Stephen Boyd 
Quoting Ryder Lee (2018-03-19 20:16:52)
> Add clock driver support for MT2701 audsys.
> 
> Signed-off-by: Ryder Lee 
> ---

Applied to clk-next

[PATCH 2/2] clk: mediatek: add audsys support for MT2701

2018-03-19 Thread Ryder Lee 
Add clock driver support for MT2701 audsys.

Signed-off-by: Ryder Lee 
---
 drivers/clk/mediatek/Kconfig  |   6 ++
 drivers/clk/mediatek/Makefile |   1 +
 drivers/clk/mediatek/clk-mt2701-aud.c | 186 ++
 3 files changed, 193 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt2701-aud.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 1f9ea0f..92afe59 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -54,6 +54,12 @@ config COMMON_CLK_MT2701_BDPSYS
---help---
  This driver supports MediaTek MT2701 bdpsys clocks.
 
+config COMMON_CLK_MT2701_AUDSYS
+   bool "Clock driver for Mediatek MT2701 audsys"
+   depends on COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 audsys clocks.
+
 config COMMON_CLK_MT2712
bool "Clock driver for MediaTek MT2712"
depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 5160fdc..b80eff2 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
 obj-$(CONFIG_COMMON_CLK_MT6797_VDECSYS) += clk-mt6797-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT6797_VENCSYS) += clk-mt6797-venc.o
 obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
+obj-$(CONFIG_COMMON_CLK_MT2701_AUDSYS) += clk-mt2701-aud.o
 obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
 obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o
 obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c 
b/drivers/clk/mediatek/clk-mt2701-aud.c
new file mode 100644
index 000..e66896a
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2701-aud.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Ryder Lee 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include 
+
+#define GATE_AUDIO0(_id, _name, _parent, _shift) { \
+   .id = _id,  \
+   .name = _name,  \
+   .parent_name = _parent, \
+   .regs = _cg_regs,\
+   .shift = _shift,\
+   .ops = _clk_gate_ops_no_setclr, \
+   }
+
+#define GATE_AUDIO1(_id, _name, _parent, _shift) { \
+   .id = _id,  \
+   .name = _name,  \
+   .parent_name = _parent, \
+   .regs = _cg_regs,\
+   .shift = _shift,\
+   .ops = _clk_gate_ops_no_setclr, \
+   }
+
+#define GATE_AUDIO2(_id, _name, _parent, _shift) { \
+   .id = _id,  \
+   .name = _name,  \
+   .parent_name = _parent, \
+   .regs = _cg_regs,\
+   .shift = _shift,\
+   .ops = _clk_gate_ops_no_setclr, \
+   }
+
+#define GATE_AUDIO3(_id, _name, _parent, _shift) { \
+   .id = _id,  \
+   .name = _name,  \
+   .parent_name = _parent, \
+   .regs = _cg_regs,\
+   .shift = _shift,\
+   .ops = _clk_gate_ops_no_setclr, \
+   }
+
+static const struct mtk_gate_regs audio0_cg_regs = {
+   .set_ofs = 0x0,
+   .clr_ofs = 0x0,
+   .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs audio1_cg_regs = {
+   .set_ofs = 0x10,
+   .clr_ofs = 0x10,
+   .sta_ofs = 0x10,
+};
+
+static const struct mtk_gate_regs audio2_cg_regs = {
+   .set_ofs = 0x14,
+   .clr_ofs = 0x14,
+   .sta_ofs = 0x14,
+};
+
+static const struct mtk_gate_regs audio3_cg_regs = {
+   .set_ofs = 0x634,
+   .clr_ofs = 0x634,
+   .sta_ofs = 0x634,
+};
+
+static const struct mtk_gate audio_clks[] = {
+   /* AUDIO0 */
+   GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
+   GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
+   GATE_AUDIO0(CLK_AUD_SPDF, "audio_spdf", "audpll_sel", 21),
+   GATE_AUDIO0(CLK_AUD_SPDF2, "audio_spdf2", "audpll_sel", 22),
+   GATE_AUDIO0(CLK_AUD_APLL, "audio_apll", "audpll_sel", 23),
+   /* AUDIO1 */
+   GATE_AUDIO1(CLK_AUD_I2SIN1, "audio_i2sin1", "aud_mux1_sel", 0),
+   GATE_AUDIO1(CLK_AUD_I2SIN2, "audio_i2sin2", "aud_mux1_sel", 1),
+   GATE_AUDIO1(CLK_AUD_I2SIN3, "audio_i2sin3", "aud_mux1_sel", 2),
+

[PATCH 2/2] clk: mediatek: add audsys support for MT2701

2018-03-19 Thread Ryder Lee 
Add clock driver support for MT2701 audsys.

Signed-off-by: Ryder Lee 
---
 drivers/clk/mediatek/Kconfig  |   6 ++
 drivers/clk/mediatek/Makefile |   1 +
 drivers/clk/mediatek/clk-mt2701-aud.c | 186 ++
 3 files changed, 193 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt2701-aud.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 1f9ea0f..92afe59 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -54,6 +54,12 @@ config COMMON_CLK_MT2701_BDPSYS
---help---
  This driver supports MediaTek MT2701 bdpsys clocks.
 
+config COMMON_CLK_MT2701_AUDSYS
+   bool "Clock driver for Mediatek MT2701 audsys"
+   depends on COMMON_CLK_MT2701
+   ---help---
+ This driver supports Mediatek MT2701 audsys clocks.
+
 config COMMON_CLK_MT2712
bool "Clock driver for MediaTek MT2712"
depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 5160fdc..b80eff2 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o
 obj-$(CONFIG_COMMON_CLK_MT6797_VDECSYS) += clk-mt6797-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT6797_VENCSYS) += clk-mt6797-venc.o
 obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
+obj-$(CONFIG_COMMON_CLK_MT2701_AUDSYS) += clk-mt2701-aud.o
 obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o
 obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o
 obj-$(CONFIG_COMMON_CLK_MT2701_HIFSYS) += clk-mt2701-hif.o
diff --git a/drivers/clk/mediatek/clk-mt2701-aud.c 
b/drivers/clk/mediatek/clk-mt2701-aud.c
new file mode 100644
index 000..e66896a
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt2701-aud.c
@@ -0,0 +1,186 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Ryder Lee 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include 
+
+#define GATE_AUDIO0(_id, _name, _parent, _shift) { \
+   .id = _id,  \
+   .name = _name,  \
+   .parent_name = _parent, \
+   .regs = _cg_regs,\
+   .shift = _shift,\
+   .ops = _clk_gate_ops_no_setclr, \
+   }
+
+#define GATE_AUDIO1(_id, _name, _parent, _shift) { \
+   .id = _id,  \
+   .name = _name,  \
+   .parent_name = _parent, \
+   .regs = _cg_regs,\
+   .shift = _shift,\
+   .ops = _clk_gate_ops_no_setclr, \
+   }
+
+#define GATE_AUDIO2(_id, _name, _parent, _shift) { \
+   .id = _id,  \
+   .name = _name,  \
+   .parent_name = _parent, \
+   .regs = _cg_regs,\
+   .shift = _shift,\
+   .ops = _clk_gate_ops_no_setclr, \
+   }
+
+#define GATE_AUDIO3(_id, _name, _parent, _shift) { \
+   .id = _id,  \
+   .name = _name,  \
+   .parent_name = _parent, \
+   .regs = _cg_regs,\
+   .shift = _shift,\
+   .ops = _clk_gate_ops_no_setclr, \
+   }
+
+static const struct mtk_gate_regs audio0_cg_regs = {
+   .set_ofs = 0x0,
+   .clr_ofs = 0x0,
+   .sta_ofs = 0x0,
+};
+
+static const struct mtk_gate_regs audio1_cg_regs = {
+   .set_ofs = 0x10,
+   .clr_ofs = 0x10,
+   .sta_ofs = 0x10,
+};
+
+static const struct mtk_gate_regs audio2_cg_regs = {
+   .set_ofs = 0x14,
+   .clr_ofs = 0x14,
+   .sta_ofs = 0x14,
+};
+
+static const struct mtk_gate_regs audio3_cg_regs = {
+   .set_ofs = 0x634,
+   .clr_ofs = 0x634,
+   .sta_ofs = 0x634,
+};
+
+static const struct mtk_gate audio_clks[] = {
+   /* AUDIO0 */
+   GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
+   GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
+   GATE_AUDIO0(CLK_AUD_SPDF, "audio_spdf", "audpll_sel", 21),
+   GATE_AUDIO0(CLK_AUD_SPDF2, "audio_spdf2", "audpll_sel", 22),
+   GATE_AUDIO0(CLK_AUD_APLL, "audio_apll", "audpll_sel", 23),
+   /* AUDIO1 */
+   GATE_AUDIO1(CLK_AUD_I2SIN1, "audio_i2sin1", "aud_mux1_sel", 0),
+   GATE_AUDIO1(CLK_AUD_I2SIN2, "audio_i2sin2", "aud_mux1_sel", 1),
+   GATE_AUDIO1(CLK_AUD_I2SIN3, "audio_i2sin3", "aud_mux1_sel", 2),
+   GATE_AUDIO1(CLK_AUD_I2SIN4, "audio_i2sin4",