Re: [PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
On 08-01-19, 20:19, Shun-Chih.Yu wrote:
> On Fri, 2019-01-04 at 18:08 +0530, Vinod Koul wrote:
> > On 27-12-18, 21:10, shun-chih...@mediatek.com wrote:
> > > From: Shun-Chih Yu
> > Have you tested this with dmatest, if so can you provide results of the
> > test as well.
> Yes, I tested with dmatest in multi-thread version.
> The results shown below, and I would attach them in the next revision if
> needed.
>
> dmatest: dma0chan0-copy2: summary 5000 tests, 0 failures 3500 iops 28037
> KB/s (0)
> dmatest: dma0chan0-copy4: summary 5000 tests, 0 failures 3494 iops 27612
> KB/s (0)
> dmatest: dma0chan0-copy1: summary 5000 tests, 0 failures 3491 iops 27749
> KB/s (0)
> dmatest: dma0chan0-copy7: summary 5000 tests, 0 failures 3673 iops 29092
> KB/s (0)
> dmatest: dma0chan0-copy6: summary 5000 tests, 0 failures 3763 iops 30237
> KB/s (0)
> dmatest: dma0chan0-copy0: summary 5000 tests, 0 failures 3730 iops 30131
> KB/s (0)
> dmatest: dma0chan0-copy3: summary 5000 tests, 0 failures 3717 iops 29569
> KB/s (0)
> dmatest: dma0chan0-copy5: summary 5000 tests, 0 failures 3699 iops 29302
> KB/s (0)
Having them in cover letter helps :)
> > > Signed-off-by: Shun-Chih Yu
> > > Reviewed-by: Vinod Koul
> >
> > This is _WRONG_ I have never provided such tag, can you explain why this
> > was added without my approval?
> So sorry about this, I misunderstood the usage of reviewed-by tag and I
> would remove this. Thanks for pointing out this mistake.
This tag should be added _only_ when someone replies with
Reviewed-by: ..., same goes for Acked-by and Tested-by: ... etc
> > > +static void mtk_dma_write(struct mtk_cqdma_pchan *pc, u32 reg, u32 val)
> > > +{
> > > + writel_relaxed(val, pc->base + reg);
> >
> > Why is it relaxed one?
> Most of the operations to the CQDMA hardware could be relaxed, and the
looks like you missed the rest of sentence
> > > +static enum dma_status mtk_cqdma_tx_status(struct dma_chan *c,
> > > +dma_cookie_t cookie,
> > > +struct dma_tx_state *txstate)
> > > +{
> > > + struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c);
> > > + struct mtk_cqdma_vdesc *cvd;
> > > + struct virt_dma_desc *vd;
> > > + enum dma_status ret;
> > > + unsigned long flags;
> > > + size_t bytes = 0;
> > > +
> > > + ret = dma_cookie_status(c, cookie, txstate);
> > > + if (ret == DMA_COMPLETE || !txstate)
> > > + return ret;
> > > +
> > > + spin_lock_irqsave(&cvc->vc.lock, flags);
> > > + vd = mtk_cqdma_find_active_desc(c, cookie);
> > > + spin_unlock_irqrestore(&cvc->vc.lock, flags);
> > > +
> > > + if (vd) {
> > > + cvd = to_cqdma_vdesc(vd);
> > > + bytes = cvd->len;
> > > + }
> > > +
> > > + dma_set_residue(txstate, bytes);
> >
> > Have you tested this and are able to report residue properly?
> >
> I tested and thought the residue report properly. But after checking the
> definition of residue in tx_status again, I found that should be always
> return 0 in the driver instead, since there is no state DMA_IN_PROGRESS
> or DMA_PAUSED in the driver. I would fix this in the next revision.
So memcpy is quite fast :D, that's why. This is more helpful in
slave-dma which is relatively slow :)
--
~Vinod
Re: [PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
On 27-12-18, 21:10, shun-chih...@mediatek.com wrote:
> From: Shun-Chih Yu
>
This should be v4 of the patch series, why is it not tagged so?
> MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
> to memory-to-memory transfer through queue based descriptor management.
Have you tested this with dmatest, if so can you provide results of the
test as well.
> There are only 3 physical channels inside CQDMA, while the driver is
> extended to support 32 virtual channels for multiple dma users to issue
> dma requests onto the CQDMA simultaneously.
>
> Change-Id: I1e8d116c5ecbbc49190ffc925cb59a0d035d886b
Please remove this from upstream, checkpatch would have warned that!
> Signed-off-by: Shun-Chih Yu
> Reviewed-by: Vinod Koul
This is _WRONG_ I have never provided such tag, can you explain why this
was added without my approval?
> This controller provides the channels which is dedicated to
> memory-to-memory transfer to offload from CPU through ring-
> based descriptor management.
> +
> +config MTK_CQDMA
> + tristate "MediaTek Command-Queue DMA controller support"
Am not sure if I asked this earlier but, what is difference with HSDMA?
> +/**
> + * struct mtk_cqdma_pchan - The struct holding info describing physical
> + * channel (PC)
> + * @queue: Queue for the CVDs issued to this PC
> + * @base: The mapped register I/O base of this PC
> + * @irq: The IRQ that this PC are using
> + * @refcnt:Track how many VCs are using this PC
> + * @lock: Lock protect agaisting multiple VCs access PC
Please maintain alignment!
> + */
> +struct mtk_cqdma_pchan {
> + struct list_head queue;
> + void __iomem *base;
> + u32 irq;
> + refcount_t refcnt;
> +
> + /* lock to protect PC */
This is not required, you already have above !
> + spinlock_t lock;
> +};
> +
> +/**
> + * struct mtk_cqdma_vchan - The struct holding info describing virtual
> + * channel (VC)
> + * @vc:An instance for struct virt_dma_chan
> + * @pc:The pointer to the underlying PC
> + * @issue_completion: The wait for all issued descriptors
> completited
typo completited , am not sure why you need this
> +static void mtk_dma_write(struct mtk_cqdma_pchan *pc, u32 reg, u32 val)
> +{
> + writel_relaxed(val, pc->base + reg);
Why is it relaxed one?
> +static void mtk_cqdma_consume_work_queue(struct mtk_cqdma_pchan *pc)
> +{
> + struct mtk_cqdma_vchan *cvc;
> + struct mtk_cqdma_vdesc *cvd;
> + size_t tlen;
> +
> + /* consume a CVD from PC's queue */
> + cvd = list_first_entry_or_null(&pc->queue,
> +struct mtk_cqdma_vdesc, node);
you can use vchan_next_desc() and also remove your own queue as
virt-desc already implements that logic!
> + if (unlikely(!cvd))
> + return;
> +
> + cvc = to_cqdma_vchan(cvd->ch);
> +
> + tlen = (cvd->len < MTK_CQDMA_MAX_LEN) ? cvd->len : MTK_CQDMA_MAX_LEN;
> + cvd->len -= tlen;
> + cvd->src += tlen;
> + cvd->dest += tlen;
> +
> + /* check whether the CVD completed */
> + if (!cvd->len) {
> + /* delete CVD from PC's queue */
> + list_del(&cvd->node);
> +
> + spin_lock(&cvc->vc.lock);
> +
> + /* add the VD into list desc_completed */
> + vchan_cookie_complete(&cvd->vd);
> +
> + /* setup completion if this VC is under synchronization */
> + if (cvc->issue_synchronize && !mtk_cqdma_is_vchan_active(cvc)) {
> + complete(&cvc->issue_completion);
> + cvc->issue_synchronize = false;
> + }
why do you need your own completion?
> +
> + spin_unlock(&cvc->vc.lock);
> + }
> +
> + /* iterate on the next CVD if the current CVD completed */
> + if (!cvd->len)
> + cvd = list_first_entry_or_null(&pc->queue,
> +struct mtk_cqdma_vdesc, node);
> +
> + /* start the next transaction */
> + if (cvd)
> + mtk_cqdma_start(pc, cvd);
most of this logic looks reduandant to me. Virt-dma was designed to do
exactly this, have N physical channels and share with M virt channels.
Please reuse and remove code from this driver.
> +static struct virt_dma_desc *mtk_cqdma_find_active_desc(struct dma_chan *c,
> + dma_cookie_t cookie)
> +{
> + struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c);
> + struct virt_dma_desc *vd;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&cvc->pc->lock, flags);
> + list_for_each_entry(vd, &cvc->pc->queue, node)
> + if (vd->tx.cookie == cookie) {
> + spin_unlock_irqrestore(&cvc->pc->lock, flags);
> + return vd;
> +
Re: [PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
go on other parts not finished review at the last time On Sat, Dec 29, 2018 at 3:03 AM Sean Wang wrote: > > The version looks like better than the earlier version, but there are > still a few nitpicks I post at the inline. > > On Thu, Dec 27, 2018 at 5:11 AM wrote: > > > > From: Shun-Chih Yu > > > > MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated > > to memory-to-memory transfer through queue based descriptor management. > > > > There are only 3 physical channels inside CQDMA, while the driver is > > extended to support 32 virtual channels for multiple dma users to issue > > dma requests onto the CQDMA simultaneously. > > > > Change-Id: I1e8d116c5ecbbc49190ffc925cb59a0d035d886b > > should be more careful drop the change-id every time > > > Signed-off-by: Shun-Chih Yu > > Reviewed-by: Vinod Koul > > > > --- > > drivers/dma/mediatek/Kconfig | 12 + > > drivers/dma/mediatek/Makefile|1 + > > drivers/dma/mediatek/mtk-cqdma.c | 867 > > ++ > > 3 files changed, 880 insertions(+) > > create mode 100644 drivers/dma/mediatek/mtk-cqdma.c > > > > diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig > > index 27bac0b..4a1582d 100644 > > --- a/drivers/dma/mediatek/Kconfig > > +++ b/drivers/dma/mediatek/Kconfig > > @@ -11,3 +11,15 @@ config MTK_HSDMA > > This controller provides the channels which is dedicated to > > memory-to-memory transfer to offload from CPU through ring- > > based descriptor management. > > + > > +config MTK_CQDMA > > + tristate "MediaTek Command-Queue DMA controller support" > > + depends on ARCH_MEDIATEK || COMPILE_TEST > > + select DMA_ENGINE > > + select DMA_VIRTUAL_CHANNELS > > + help > > + Enable support for Command-Queue DMA controller on MediaTek > > + SoCs. > > + > > + This controller provides the channels which is dedicated to > > + memory-to-memory transfer to offload from CPU. > > diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile > > index 6e778f8..41bb381 100644 > > --- a/drivers/dma/mediatek/Makefile > > +++ b/drivers/dma/mediatek/Makefile > > @@ -1 +1,2 @@ > > obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o > > +obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o > > diff --git a/drivers/dma/mediatek/mtk-cqdma.c > > b/drivers/dma/mediatek/mtk-cqdma.c > > new file mode 100644 > > index 000..304eb0a > > --- /dev/null > > +++ b/drivers/dma/mediatek/mtk-cqdma.c > > @@ -0,0 +1,867 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// Copyright (c) 2018-2019 MediaTek Inc. > > + > > +/* > > + * Driver for MediaTek Command-Queue DMA Controller > > + * > > + * Author: Shun-Chih Yu > > + * > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#include "../virt-dma.h" > > + > > +#define MTK_CQDMA_USEC_POLL10 > > +#define MTK_CQDMA_TIMEOUT_POLL 1000 > > +#define MTK_CQDMA_DMA_BUSWIDTHS > > BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) > > +#define MTK_CQDMA_ALIGN_SIZE 1 > > + > > +/* The default number of virtual channel */ > > +#define MTK_CQDMA_NR_VCHANS32 > > + > > +/* The default number of physical channel */ > > +#define MTK_CQDMA_NR_PCHANS3 > > + > > +/* Registers for underlying dma manipulation */ > > +#define MTK_CQDMA_INT_FLAG 0x0 > > +#define MTK_CQDMA_INT_EN 0x4 > > +#define MTK_CQDMA_EN 0x8 > > +#define MTK_CQDMA_RESET0xc > > +#define MTK_CQDMA_FLUSH0x14 > > +#define MTK_CQDMA_SRC 0x1c > > +#define MTK_CQDMA_DST 0x20 > > +#define MTK_CQDMA_LEN1 0x24 > > +#define MTK_CQDMA_LEN2 0x28 > > drop unused macro and check if it happens at other places > > > +#define MTK_CQDMA_SRC2 0x60 > > +#define MTK_CQDMA_DST2 0x64 > > + > > +/* Registers setting */ > > +#define MTK_CQDMA_EN_BIT BIT(0) > > +#define MTK_CQDMA_INT_FLAG_BIT BIT(0) > > +#define MTK_CQDMA_INT_EN_BIT BIT(0) > > +#define MTK_CQDMA_FLUSH_BITBIT(0) > > + > > +#define MTK_CQDMA_WARM_RST_BIT BIT(0) > > +#define MTK_CQDMA_HARD_RST_BIT BIT(1) > > + > > +#define MTK_CQDMA_MAX_LEN GENMASK(27, 0) > > +#define MTK_CQDMA_ADDR_LIMIT GENMASK(31, 0) > > +#define MTK_CQDMA_ADDR2_SHFIT (32) > > + > > +/** > > + * struct mtk_cqdma_vdesc - The struct holding info describing virtual > > + * descriptor (CVD) > > + * @vd:An instance for struct virt_dma_desc > > + * @len: The total data size device wants to move > > + * @dest: The de
[PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
From: Shun-Chih Yu
MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
to memory-to-memory transfer through queue based descriptor management.
There are only 3 physical channels inside CQDMA, while the driver is
extended to support 32 virtual channels for multiple dma users to issue
dma requests onto the CQDMA simultaneously.
Change-Id: I1e8d116c5ecbbc49190ffc925cb59a0d035d886b
Signed-off-by: Shun-Chih Yu
Reviewed-by: Vinod Koul
---
drivers/dma/mediatek/Kconfig | 12 +
drivers/dma/mediatek/Makefile|1 +
drivers/dma/mediatek/mtk-cqdma.c | 867 ++
3 files changed, 880 insertions(+)
create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
index 27bac0b..4a1582d 100644
--- a/drivers/dma/mediatek/Kconfig
+++ b/drivers/dma/mediatek/Kconfig
@@ -11,3 +11,15 @@ config MTK_HSDMA
This controller provides the channels which is dedicated to
memory-to-memory transfer to offload from CPU through ring-
based descriptor management.
+
+config MTK_CQDMA
+ tristate "MediaTek Command-Queue DMA controller support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ Enable support for Command-Queue DMA controller on MediaTek
+ SoCs.
+
+ This controller provides the channels which is dedicated to
+ memory-to-memory transfer to offload from CPU.
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
index 6e778f8..41bb381 100644
--- a/drivers/dma/mediatek/Makefile
+++ b/drivers/dma/mediatek/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
+obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
new file mode 100644
index 000..304eb0a
--- /dev/null
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -0,0 +1,867 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018-2019 MediaTek Inc.
+
+/*
+ * Driver for MediaTek Command-Queue DMA Controller
+ *
+ * Author: Shun-Chih Yu
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+
+#define MTK_CQDMA_USEC_POLL10
+#define MTK_CQDMA_TIMEOUT_POLL 1000
+#define MTK_CQDMA_DMA_BUSWIDTHSBIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+#define MTK_CQDMA_ALIGN_SIZE 1
+
+/* The default number of virtual channel */
+#define MTK_CQDMA_NR_VCHANS32
+
+/* The default number of physical channel */
+#define MTK_CQDMA_NR_PCHANS3
+
+/* Registers for underlying dma manipulation */
+#define MTK_CQDMA_INT_FLAG 0x0
+#define MTK_CQDMA_INT_EN 0x4
+#define MTK_CQDMA_EN 0x8
+#define MTK_CQDMA_RESET0xc
+#define MTK_CQDMA_FLUSH0x14
+#define MTK_CQDMA_SRC 0x1c
+#define MTK_CQDMA_DST 0x20
+#define MTK_CQDMA_LEN1 0x24
+#define MTK_CQDMA_LEN2 0x28
+#define MTK_CQDMA_SRC2 0x60
+#define MTK_CQDMA_DST2 0x64
+
+/* Registers setting */
+#define MTK_CQDMA_EN_BIT BIT(0)
+#define MTK_CQDMA_INT_FLAG_BIT BIT(0)
+#define MTK_CQDMA_INT_EN_BIT BIT(0)
+#define MTK_CQDMA_FLUSH_BITBIT(0)
+
+#define MTK_CQDMA_WARM_RST_BIT BIT(0)
+#define MTK_CQDMA_HARD_RST_BIT BIT(1)
+
+#define MTK_CQDMA_MAX_LEN GENMASK(27, 0)
+#define MTK_CQDMA_ADDR_LIMIT GENMASK(31, 0)
+#define MTK_CQDMA_ADDR2_SHFIT (32)
+
+/**
+ * struct mtk_cqdma_vdesc - The struct holding info describing virtual
+ * descriptor (CVD)
+ * @vd:An instance for struct virt_dma_desc
+ * @len: The total data size device wants to move
+ * @dest: The destination address device wants to move to
+ * @src: The source address device wants to move from
+ * @ch:The pointer to the corresponding dma channel
+ * @node: To build linked-list for PC queue
+ */
+struct mtk_cqdma_vdesc {
+ struct virt_dma_desc vd;
+ size_t len;
+ dma_addr_t dest;
+ dma_addr_t src;
+ struct dma_chan *ch;
+
+ /* protected by pc.lock */
+ struct list_head node;
+};
+
+/**
+ * struct mtk_cqdma_pchan - The struct holding info describing physical
+ * channel (PC)
+ * @queue: Queue for the CVDs issued to this PC
+ * @base: The mapped register I/O base of this PC
+ * @irq: The IRQ that this PC are using
+ * @refcnt:Track how many VCs are using this PC
+ * @lock: Lock protect agai
Re: [PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
On 18-10-18, 15:49, shun-chih...@mediatek.com wrote:
> From: Shun-Chih Yu
>
> MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
> to memory-to-memory transfer through queue based descriptor management.
>
> There are only 3 physical channels inside CQDMA, while the driver is
> extended to support 32 virtual channels for multiple dma users to issue
> dma requests onto the CQDMA simultaneously.
I see some warns in the driver when I compile with C=1 please do fix
those in next rev
> +struct mtk_cqdma_vdesc {
> + struct virt_dma_desc vd;
> + size_t len;
> + size_t residue;
why should you store residue in descriptor, it will get stale very soon!
> + dma_addr_t dest;
> + dma_addr_t src;
> + struct dma_chan *ch;
> +
> + struct list_head node;
why do you need your own list, vd has a list for descriptors!
> +struct mtk_cqdma_pchan {
> + struct list_head queue;
> + void __iomem *base;
> + u32 irq;
> +
> + refcount_t refcnt;
Can you submit more than one descriptor at any point of time?
> +struct mtk_cqdma_vchan {
> + struct virt_dma_chan vc;
> + struct mtk_cqdma_pchan *pc;
> + struct completion issue_completion;
> + bool issue_synchronize;
what lock protects this?
> +static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc,
> + struct mtk_cqdma_vdesc *cvd)
> +{
> + /* wait for the previous transaction done */
> + if (mtk_cqdma_poll_engine_done(pc, true) < 0)
> + dev_err(cqdma2dev(to_cqdma_dev(cvd->ch)), "cqdma wait
> transaction timeout\n");
Please split this to 2 lines to adhere to 80 chars limit
Also no bailout of error?
> +static struct mtk_cqdma_vdesc
> +*mtk_cqdma_consume_work_queue(struct mtk_cqdma_pchan *pc)
> +{
> + struct mtk_cqdma_vchan *cvc;
> + struct mtk_cqdma_vdesc *cvd, *ret = NULL;
ret initialization seems superfluous
> +static void mtk_cqdma_tasklet_cb(unsigned long data)
> +{
> + struct mtk_cqdma_pchan *pc = (struct mtk_cqdma_pchan *)data;
> + struct mtk_cqdma_vdesc *cvd = NULL;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&pc->lock, flags);
> + /* consume the queue */
> + cvd = mtk_cqdma_consume_work_queue(pc);
why not do this from ISR, DMA should be submitted as fast as possible!
> +static int mtk_cqdma_alloc_chan_resources(struct dma_chan *c)
> +{
> + struct mtk_cqdma_device *cqdma = to_cqdma_dev(c);
> + struct mtk_cqdma_vchan *vc = to_cqdma_vchan(c);
> + struct mtk_cqdma_pchan *pc = NULL;
> + u32 i, min_refcnt = U32_MAX, refcnt;
> + unsigned long flags;
> +
> + /* allocate PC with the minimun refcount */
^^^
typo
> +static int mtk_cqdma_probe(struct platform_device *pdev)
> +{
> + struct mtk_cqdma_device *cqdma;
> + struct mtk_cqdma_vchan *vc;
> + struct dma_device *dd;
> + struct resource *res;
> + int err;
> + u32 i;
> +
> + cqdma = devm_kzalloc(&pdev->dev, sizeof(*cqdma), GFP_KERNEL);
> + if (!cqdma)
> + return -ENOMEM;
> +
> + dd = &cqdma->ddev;
> +
> + cqdma->clk = devm_clk_get(&pdev->dev, "cqdma");
> + if (IS_ERR(cqdma->clk)) {
> + dev_err(&pdev->dev, "No clock for %s\n",
> + dev_name(&pdev->dev));
> + return PTR_ERR(cqdma->clk);
> + }
> +
> + dma_cap_set(DMA_MEMCPY, dd->cap_mask);
> +
> + dd->copy_align = MTK_CQDMA_ALIGN_SIZE;
> + dd->device_alloc_chan_resources = mtk_cqdma_alloc_chan_resources;
> + dd->device_free_chan_resources = mtk_cqdma_free_chan_resources;
> + dd->device_tx_status = mtk_cqdma_tx_status;
> + dd->device_issue_pending = mtk_cqdma_issue_pending;
> + dd->device_prep_dma_memcpy = mtk_cqdma_prep_dma_memcpy;
> + dd->device_terminate_all = mtk_cqdma_terminate_all;
> + dd->src_addr_widths = MTK_CQDMA_DMA_BUSWIDTHS;
> + dd->dst_addr_widths = MTK_CQDMA_DMA_BUSWIDTHS;
> + dd->directions = BIT(DMA_MEM_TO_MEM);
> + dd->residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
> + dd->dev = &pdev->dev;
> + INIT_LIST_HEAD(&dd->channels);
> +
> + if (pdev->dev.of_node && of_property_read_u32(pdev->dev.of_node,
> + "dma-requests",
> + &cqdma->dma_requests)) {
> + dev_info(&pdev->dev,
> + "Using %u as missing dma-requests property\n",
> + MTK_CQDMA_NR_VCHANS);
> +
> + cqdma->dma_requests = MTK_CQDMA_NR_VCHANS;
> + }
> +
> + if (pdev->dev.of_node && of_property_read_u32(pdev->dev.of_node,
> + "dma-channels",
> + &cqdma->dma_channels)) {
> + dev_info(&pdev->dev,
> + "Using %u as missing dma-channels property\n",
> + MTK_CQDMA_NR_PCHANS);
> +
> + cqdma->dma
[PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
From: Shun-Chih Yu
MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
to memory-to-memory transfer through queue based descriptor management.
There are only 3 physical channels inside CQDMA, while the driver is
extended to support 32 virtual channels for multiple dma users to issue
dma requests onto the CQDMA simultaneously.
Signed-off-by: Shun-Chih Yu
---
drivers/dma/mediatek/Kconfig | 13 +
drivers/dma/mediatek/Makefile|1 +
drivers/dma/mediatek/mtk-cqdma.c | 951 ++
3 files changed, 965 insertions(+)
create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
index 27bac0b..680fc05 100644
--- a/drivers/dma/mediatek/Kconfig
+++ b/drivers/dma/mediatek/Kconfig
@@ -11,3 +11,16 @@ config MTK_HSDMA
This controller provides the channels which is dedicated to
memory-to-memory transfer to offload from CPU through ring-
based descriptor management.
+
+config MTK_CQDMA
+ tristate "MediaTek Command-Queue DMA controller support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ select ASYNC_TX_ENABLE_CHANNEL_SWITCH
+ help
+ Enable support for Command-Queue DMA controller on MediaTek
+ SoCs.
+
+ This controller provides the channels which is dedicated to
+ memory-to-memory transfer to offload from CPU.
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
index 6e778f8..41bb381 100644
--- a/drivers/dma/mediatek/Makefile
+++ b/drivers/dma/mediatek/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
+obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
new file mode 100644
index 000..131f397
--- /dev/null
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -0,0 +1,951 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018-2019 MediaTek Inc.
+
+/*
+ * Driver for MediaTek Command-Queue DMA Controller
+ *
+ * Author: Shun-Chih Yu
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+
+#define MTK_CQDMA_USEC_POLL10
+#define MTK_CQDMA_TIMEOUT_POLL 1000
+#define MTK_CQDMA_DMA_BUSWIDTHSBIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+#define MTK_CQDMA_ALIGN_SIZE 1
+
+/* The default number of virtual channel */
+#define MTK_CQDMA_NR_VCHANS32
+
+/* The default number of physical channel */
+#define MTK_CQDMA_NR_PCHANS3
+
+/* Registers for underlying dma manipulation */
+#define MTK_CQDMA_INT_FLAG 0x0
+#define MTK_CQDMA_INT_EN 0x4
+#define MTK_CQDMA_EN 0x8
+#define MTK_CQDMA_RESET0xc
+#define MTK_CQDMA_FLUSH0x14
+#define MTK_CQDMA_SRC 0x1c
+#define MTK_CQDMA_DST 0x20
+#define MTK_CQDMA_LEN1 0x24
+#define MTK_CQDMA_LEN2 0x28
+#define MTK_CQDMA_SRC2 0x60
+#define MTK_CQDMA_DST2 0x64
+
+/* Registers setting */
+#define MTK_CQDMA_EN_BIT BIT(0)
+#define MTK_CQDMA_INT_FLAG_BIT BIT(0)
+#define MTK_CQDMA_INT_EN_BIT BIT(0)
+#define MTK_CQDMA_FLUSH_BITBIT(0)
+
+#define MTK_CQDMA_WARM_RST_BIT BIT(0)
+#define MTK_CQDMA_HARD_RST_BIT BIT(1)
+
+#define MTK_CQDMA_MAX_LEN GENMASK(27, 0)
+#define MTK_CQDMA_ADDR_LIMIT GENMASK(31, 0)
+#define MTK_CQDMA_ADDR2_SHFIT (32)
+
+/**
+ * struct mtk_cqdma_vdesc - The struct holding info describing virtual
+ * descriptor (CVD)
+ * @vd:An instance for struct virt_dma_desc
+ * @len: The total data size device wants to move
+ * @residue: The remaining data size device will move
+ * @dest: The destination address device wants to move to
+ * @src: The source address device wants to move from
+ * @ch:The pointer to the corresponding dma channel
+ * @node: The lise_head struct to build link-list for VDs
+ * @parent:The pointer to the parent CVD
+ */
+struct mtk_cqdma_vdesc {
+ struct virt_dma_desc vd;
+ size_t len;
+ size_t residue;
+ dma_addr_t dest;
+ dma_addr_t src;
+ struct dma_chan *ch;
+
+ struct list_head node;
+ struct mtk_cqdma_vdesc *parent;
+};
+
+/**
+ * struct mtk_cqdma_pchan - The struct holding info describing physical
+ * channel (PC)
+ * @queue: Queue for the PDs issued to this PC
+ * @base: The mapped register I/O base of this PC
+ * @irq: The
Re: [PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
Hi Shun-Chih,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linux-sof-driver/master]
[also build test WARNING on v4.19-rc8 next-20181017]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits/shun-chih-yu-mediatek-com/dt-bindings-dmaengine-Add-MediaTek-Command-Queue-DMA-controller-bindings/20181018-071645
base: https://github.com/thesofproject/linux master
config: i386-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All warnings (new ones prefixed by >>):
drivers/dma/mediatek/mtk-cqdma.c: In function 'mtk_cqdma_start':
>> drivers/dma/mediatek/mtk-cqdma.c:245:43: warning: right shift count >= width
>> of type [-Wshift-count-overflow]
mtk_dma_set(pc, MTK_CQDMA_SRC2, cvd->src >> MTK_CQDMA_ADDR2_SHFIT);
^~
drivers/dma/mediatek/mtk-cqdma.c:249:44: warning: right shift count >= width
of type [-Wshift-count-overflow]
mtk_dma_set(pc, MTK_CQDMA_DST2, cvd->dest >> MTK_CQDMA_ADDR2_SHFIT);
^~
vim +245 drivers/dma/mediatek/mtk-cqdma.c
230
231 static void mtk_cqdma_start(struct mtk_cqdma_pchan *pc,
232 struct mtk_cqdma_vdesc *cvd)
233 {
234 /* wait for the previous transaction done */
235 if (mtk_cqdma_poll_engine_done(pc, true) < 0)
236 dev_err(cqdma2dev(to_cqdma_dev(cvd->ch)), "cqdma wait
transaction timeout\n");
237
238 /* warm reset the dma engine for the new transaction */
239 mtk_dma_set(pc, MTK_CQDMA_RESET, MTK_CQDMA_WARM_RST_BIT);
240 if (mtk_cqdma_poll_engine_done(pc, true) < 0)
241 dev_err(cqdma2dev(to_cqdma_dev(cvd->ch)), "cqdma warm
reset timeout\n");
242
243 /* setup the source */
244 mtk_dma_set(pc, MTK_CQDMA_SRC, cvd->src & MTK_CQDMA_ADDR_LIMIT);
> 245 mtk_dma_set(pc, MTK_CQDMA_SRC2, cvd->src >>
> MTK_CQDMA_ADDR2_SHFIT);
246
247 /* setup the destination */
248 mtk_dma_set(pc, MTK_CQDMA_DST, cvd->dest &
MTK_CQDMA_ADDR_LIMIT);
249 mtk_dma_set(pc, MTK_CQDMA_DST2, cvd->dest >>
MTK_CQDMA_ADDR2_SHFIT);
250
251 /* setup the length */
252 mtk_dma_set(pc, MTK_CQDMA_LEN1, cvd->len);
253
254 /* start dma engine */
255 mtk_dma_set(pc, MTK_CQDMA_EN, MTK_CQDMA_EN_BIT);
256 }
257
---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
.config.gz
Description: application/gzip
[PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
From: Shun-Chih Yu
MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
to memory-to-memory transfer through queue based descriptor management.
There are only 3 physical channels inside CQDMA, while the driver is
extended to support 32 virtual channels for multiple dma users to issue
dma requests onto the CQDMA simultaneously.
Signed-off-by: Shun-Chih Yu
---
drivers/dma/mediatek/Kconfig | 13 +
drivers/dma/mediatek/Makefile|1 +
drivers/dma/mediatek/mtk-cqdma.c | 943 ++
3 files changed, 957 insertions(+)
create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
index 27bac0b..680fc05 100644
--- a/drivers/dma/mediatek/Kconfig
+++ b/drivers/dma/mediatek/Kconfig
@@ -11,3 +11,16 @@ config MTK_HSDMA
This controller provides the channels which is dedicated to
memory-to-memory transfer to offload from CPU through ring-
based descriptor management.
+
+config MTK_CQDMA
+ tristate "MediaTek Command-Queue DMA controller support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ select ASYNC_TX_ENABLE_CHANNEL_SWITCH
+ help
+ Enable support for Command-Queue DMA controller on MediaTek
+ SoCs.
+
+ This controller provides the channels which is dedicated to
+ memory-to-memory transfer to offload from CPU.
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
index 6e778f8..41bb381 100644
--- a/drivers/dma/mediatek/Makefile
+++ b/drivers/dma/mediatek/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
+obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
new file mode 100644
index 000..310ecc5
--- /dev/null
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -0,0 +1,943 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018-2019 MediaTek Inc.
+
+/*
+ * Driver for MediaTek Command-Queue DMA Controller
+ *
+ * Author: Shun-Chih Yu
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+
+#define MTK_CQDMA_USEC_POLL10
+#define MTK_CQDMA_TIMEOUT_POLL 1000
+#define MTK_CQDMA_DMA_BUSWIDTHSBIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+#define MTK_CQDMA_ALIGN_SIZE 1
+
+/* The default number of virtual channel */
+#define MTK_CQDMA_NR_VCHANS32
+
+/* The default number of physical channel */
+#define MTK_CQDMA_NR_PCHANS3
+
+/* Registers for underlying dma manipulation */
+#define MTK_CQDMA_INT_FLAG 0x0
+#define MTK_CQDMA_INT_EN 0x4
+#define MTK_CQDMA_EN 0x8
+#define MTK_CQDMA_RESET0xc
+#define MTK_CQDMA_FLUSH0x14
+#define MTK_CQDMA_SRC 0x1c
+#define MTK_CQDMA_DST 0x20
+#define MTK_CQDMA_LEN1 0x24
+#define MTK_CQDMA_LEN2 0x28
+#define MTK_CQDMA_SRC2 0x60
+#define MTK_CQDMA_DST2 0x64
+
+/* Registers setting */
+#define MTK_CQDMA_EN_BIT BIT(0)
+#define MTK_CQDMA_INT_FLAG_BIT BIT(0)
+#define MTK_CQDMA_INT_EN_BIT BIT(0)
+#define MTK_CQDMA_FLUSH_BITBIT(0)
+
+#define MTK_CQDMA_WARM_RST_BIT BIT(0)
+#define MTK_CQDMA_HARD_RST_BIT BIT(1)
+
+#define MTK_CQDMA_MAX_LEN GENMASK(27, 0)
+#define MTK_CQDMA_ADDR_LIMIT GENMASK(31, 0)
+#define MTK_CQDMA_ADDR2_SHFIT (32)
+
+/**
+ * struct mtk_cqdma_vdesc - The struct holding info describing virtual
+ * descriptor (CVD)
+ * @vd:An instance for struct virt_dma_desc
+ * @len: The total data size device wants to move
+ * @residue: The remaining data size device will move
+ * @dest: The destination address device wants to move to
+ * @src: The source address device wants to move from
+ * @ch:The pointer to the corresponding dma channel
+ * @node: The lise_head struct to build link-list for VDs
+ * @parent:The pointer to the parent CVD
+ */
+struct mtk_cqdma_vdesc {
+ struct virt_dma_desc vd;
+ size_t len;
+ size_t residue;
+ dma_addr_t dest;
+ dma_addr_t src;
+ struct dma_chan *ch;
+
+ struct list_head node;
+ struct mtk_cqdma_vdesc *parent;
+};
+
+/**
+ * struct mtk_cqdma_pchan - The struct holding info describing physical
+ * channel (PC)
+ * @queue: Queue for the PDs issued to this PC
+ * @base: The mapped register I/O base of this PC
+ * @irq: The
Re: [PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
On Tue, 2018-09-04 at 16:43 +0800, shun-chih...@mediatek.com wrote:
> From: Shun-Chih Yu
>
> MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
> to memory-to-memory transfer through queue based descriptor management.
>
> There are only 3 physical channels inside CQDMA, while the driver is
> extended to support 32 virtual channels for multiple dma users to issue
> dma requests onto the CQDMA simultaneously.
>
> Signed-off-by: Shun-Chih Yu
> ---
> drivers/dma/mediatek/Kconfig | 12 +
> drivers/dma/mediatek/Makefile|1 +
> drivers/dma/mediatek/mtk-cqdma.c | 952
> ++
> 3 files changed, 965 insertions(+)
> create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
>
> diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
> index 27bac0b..4a1582d 100644
> --- a/drivers/dma/mediatek/Kconfig
> +++ b/drivers/dma/mediatek/Kconfig
> @@ -11,3 +11,15 @@ config MTK_HSDMA
> This controller provides the channels which is dedicated to
> memory-to-memory transfer to offload from CPU through ring-
> based descriptor management.
> +
> +config MTK_CQDMA
> + tristate "MediaTek Command-Queue DMA controller support"
> + depends on ARCH_MEDIATEK || COMPILE_TEST
> + select DMA_ENGINE
> + select DMA_VIRTUAL_CHANNELS
> + help
> + Enable support for Command-Queue DMA controller on MediaTek
> + SoCs.
> +
> + This controller provides the channels which is dedicated to
> + memory-to-memory transfer to offload from CPU.
> diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
> index 6e778f8..41bb381 100644
> --- a/drivers/dma/mediatek/Makefile
> +++ b/drivers/dma/mediatek/Makefile
> @@ -1 +1,2 @@
> obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
> +obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
> diff --git a/drivers/dma/mediatek/mtk-cqdma.c
> b/drivers/dma/mediatek/mtk-cqdma.c
> new file mode 100644
> index 000..c74aaa3
> --- /dev/null
> +++ b/drivers/dma/mediatek/mtk-cqdma.c
> @@ -0,0 +1,952 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2018-2019 MediaTek Inc.
> +
> +/*
> + * Driver for MediaTek Command-Queue DMA Controller
> + *
> + * Author: Shun-Chih Yu
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "../virt-dma.h"
> +
> +#define MTK_CQDMA_USEC_POLL 10
> +#define MTK_CQDMA_TIMEOUT_POLL 1000
> +#define MTK_CQDMA_DMA_BUSWIDTHS BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
> +#define MTK_CQDMA_ALIGN_SIZE 1
> +
> +/* The default number of virtual channel */
> +#define MTK_CQDMA_NR_VCHANS 3
> +
commit message mentions there are 32 virtual channels available
> +/* The default number of physical channel */
> +#define MTK_CQDMA_NR_PCHANS 3
> +
> +/* Registers for underlying dma manipulation */
> +#define MTK_CQDMA_INT_FLAG 0x0
> +#define MTK_CQDMA_INT_EN 0x4
> +#define MTK_CQDMA_EN 0x8
> +#define MTK_CQDMA_RESET 0xc
> +#define MTK_CQDMA_STOP 0x10
> +#define MTK_CQDMA_FLUSH 0x14
> +#define MTK_CQDMA_SRC0x1c
> +#define MTK_CQDMA_DST0x20
> +#define MTK_CQDMA_LEN1 0x24
> +#define MTK_CQDMA_LEN2 0x28
> +#define MTK_CQDMA_SRC2 0x60
> +#define MTK_CQDMA_DST2 0x64
> +
> +/* Registers setting */
> +#define MTK_CQDMA_EN_BIT BIT(0)
> +#define MTK_CQDMA_INT_FLAG_BIT BIT(0)
> +#define MTK_CQDMA_INT_EN_BIT BIT(0)
> +#define MTK_CQDMA_FLUSH_BIT BIT(0)
> +
> +#define MTK_CQDMA_WARM_RST_BIT BIT(0)
> +#define MTK_CQDMA_HARD_RST_BIT BIT(1)
> +
> +#define MTK_CQDMA_MAX_LEN(0xfff)
> +#define MTK_CQDMA_ADDR_LIMIT (0x)
> +#define MTK_CQDMA_ADDR2_SHFIT(32)
remove these unused macros
> +
> +/**
> + * struct mtk_cqdma_vdesc - The struct holding info describing physical
> + * descriptor (PD)
> + * @len: The total data size device wants to move
> + * @src: The source address device wants to move from
> + * @dest: The destination address device wants to move to
> + */
> +struct mtk_cqdma_pdesc {
> + size_t len;
> + dma_addr_t src;
> + dma_addr_t dest;
> +};
> +
> +/**
> + * struct mtk_cqdma_vdesc - The struct holding info describing virtual
> + * descriptor (VD)
> + * @vd:An instance for struct virt_dma_desc
> + * @len: The total data size device wants to move
> + * @residue: The remaining data size device will move
> + * @dest:
[PATCH 2/2] dmaengine: mediatek: Add MediaTek Command-Queue DMA controller for MT6765 SoC
From: Shun-Chih Yu
MediaTek Command-Queue DMA controller (CQDMA) on MT6765 SoC is dedicated
to memory-to-memory transfer through queue based descriptor management.
There are only 3 physical channels inside CQDMA, while the driver is
extended to support 32 virtual channels for multiple dma users to issue
dma requests onto the CQDMA simultaneously.
Signed-off-by: Shun-Chih Yu
---
drivers/dma/mediatek/Kconfig | 12 +
drivers/dma/mediatek/Makefile|1 +
drivers/dma/mediatek/mtk-cqdma.c | 952 ++
3 files changed, 965 insertions(+)
create mode 100644 drivers/dma/mediatek/mtk-cqdma.c
diff --git a/drivers/dma/mediatek/Kconfig b/drivers/dma/mediatek/Kconfig
index 27bac0b..4a1582d 100644
--- a/drivers/dma/mediatek/Kconfig
+++ b/drivers/dma/mediatek/Kconfig
@@ -11,3 +11,15 @@ config MTK_HSDMA
This controller provides the channels which is dedicated to
memory-to-memory transfer to offload from CPU through ring-
based descriptor management.
+
+config MTK_CQDMA
+ tristate "MediaTek Command-Queue DMA controller support"
+ depends on ARCH_MEDIATEK || COMPILE_TEST
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ Enable support for Command-Queue DMA controller on MediaTek
+ SoCs.
+
+ This controller provides the channels which is dedicated to
+ memory-to-memory transfer to offload from CPU.
diff --git a/drivers/dma/mediatek/Makefile b/drivers/dma/mediatek/Makefile
index 6e778f8..41bb381 100644
--- a/drivers/dma/mediatek/Makefile
+++ b/drivers/dma/mediatek/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_MTK_HSDMA) += mtk-hsdma.o
+obj-$(CONFIG_MTK_CQDMA) += mtk-cqdma.o
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
new file mode 100644
index 000..c74aaa3
--- /dev/null
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -0,0 +1,952 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018-2019 MediaTek Inc.
+
+/*
+ * Driver for MediaTek Command-Queue DMA Controller
+ *
+ * Author: Shun-Chih Yu
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "../virt-dma.h"
+
+#define MTK_CQDMA_USEC_POLL10
+#define MTK_CQDMA_TIMEOUT_POLL 1000
+#define MTK_CQDMA_DMA_BUSWIDTHSBIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
+#define MTK_CQDMA_ALIGN_SIZE 1
+
+/* The default number of virtual channel */
+#define MTK_CQDMA_NR_VCHANS3
+
+/* The default number of physical channel */
+#define MTK_CQDMA_NR_PCHANS3
+
+/* Registers for underlying dma manipulation */
+#define MTK_CQDMA_INT_FLAG 0x0
+#define MTK_CQDMA_INT_EN 0x4
+#define MTK_CQDMA_EN 0x8
+#define MTK_CQDMA_RESET0xc
+#define MTK_CQDMA_STOP 0x10
+#define MTK_CQDMA_FLUSH0x14
+#define MTK_CQDMA_SRC 0x1c
+#define MTK_CQDMA_DST 0x20
+#define MTK_CQDMA_LEN1 0x24
+#define MTK_CQDMA_LEN2 0x28
+#define MTK_CQDMA_SRC2 0x60
+#define MTK_CQDMA_DST2 0x64
+
+/* Registers setting */
+#define MTK_CQDMA_EN_BIT BIT(0)
+#define MTK_CQDMA_INT_FLAG_BIT BIT(0)
+#define MTK_CQDMA_INT_EN_BIT BIT(0)
+#define MTK_CQDMA_FLUSH_BITBIT(0)
+
+#define MTK_CQDMA_WARM_RST_BIT BIT(0)
+#define MTK_CQDMA_HARD_RST_BIT BIT(1)
+
+#define MTK_CQDMA_MAX_LEN (0xfff)
+#define MTK_CQDMA_ADDR_LIMIT (0x)
+#define MTK_CQDMA_ADDR2_SHFIT (32)
+
+/**
+ * struct mtk_cqdma_vdesc - The struct holding info describing physical
+ * descriptor (PD)
+ * @len: The total data size device wants to move
+ * @src: The source address device wants to move from
+ * @dest: The destination address device wants to move to
+ */
+struct mtk_cqdma_pdesc {
+ size_t len;
+ dma_addr_t src;
+ dma_addr_t dest;
+};
+
+/**
+ * struct mtk_cqdma_vdesc - The struct holding info describing virtual
+ * descriptor (VD)
+ * @vd:An instance for struct virt_dma_desc
+ * @len: The total data size device wants to move
+ * @residue: The remaining data size device will move
+ * @dest: The destination address device wants to move to
+ * @src: The source address device wants to move from
+ * @ch:The pointer to the corresponding dma channel
+ * @pd_list The array for PDs
+ * @pd_list_len The size of PD list
+ * @pd_list_ptrThe index of the PD being processed
+ * @node The lise_head struct to build link-list for VDs
+ */
+struct mt
