subject:"\[PATCH 2\/2\] pci, pcie\-thunder\-pem\: Add PCIe host driver for ThunderX processors."

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

2015-12-22 Thread Rob Herring

On Mon, Dec 21, 2015 at 05:53:42PM -0800, David Daney wrote:
> From: David Daney 
> 
> Some Cavium ThunderX processors require quirky access methods for the
> config space of the PCIe bridge.  Add a driver to provide these config
> space accessor functions.  The pci-host-generic driver code is used to
> configure the PCI machinery.
> 
> Signed-off-by: David Daney 
> ---
>  .../devicetree/bindings/pci/pcie-thunder-pem.txt   |  43 
>  drivers/pci/host/Kconfig   |   6 +
>  drivers/pci/host/Makefile  |   1 +
>  drivers/pci/host/pcie-thunder-pem.c| 283 
> +
>  4 files changed, 333 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
>  create mode 100644 drivers/pci/host/pcie-thunder-pem.c
> 
> diff --git a/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt 
> b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
> new file mode 100644
> index 000..66824d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
> @@ -0,0 +1,43 @@
> +* ThunderX PEM PCIe host controller
> +
> +Firmware-initialized PCIe host controller found on some Cavium
> +ThunderX processors.
> +
> +The properties and their meanings are identical to those described in
> +host-heneric-pci.txt except as listed below.

s/heneric/generic/

> +
> +Properties of the host controller node that differ from
> +host-heneric-pci.txt:

ditto

> +
> +- compatible : Must be "cavium,pci-host-thunder-pem"

pcie rather than pci?


> +
> +- reg: Two entries: First the configuration space for down
> +   stream devices base address and size, as accessed
> +   from the parent bus. Second, the register bank of
> +   the PEM device PCIe bridge.
> +
> +Example:
> +
> +pem2 {

pcie-controller@...

> + compatible = "cavium,pci-host-thunder-pem";
> + device_type = "pci";
> + msi-parent = <>;
> + msi-map = <0  0x1 0x1>;
> + bus-range = <0x8f 0xc7>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> +
> + reg = <0x8880 0x8f00 0x0 0x3900>,  /* Configuration space */
> +   <0x87e0 0xc200 0x0 0x0001>; /* PEM space */
> + ranges = <0x0100 0x00 0x0002 0x88b0 0x0002 0x00 
> 0x0001>, /* I/O */
> +  <0x0300 0x00 0x1000 0x8890 0x1000 0x0f 
> 0xf000>, /* mem64 */
> +  <0x4300 0x10 0x 0x88a0 0x 0x10 
> 0x>, /* mem64-pref */
> +  <0x0300 0x87e0 0xc2f0 0x87e0 0xc200 0x00 
> 0x0010>; /* mem64 PEM BAR4 */
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1  0 0 0 24 4>, /* INTA */
> + <0 0 0 2  0 0 0 25 4>, /* INTB */
> + <0 0 0 3  0 0 0 26 4>, /* INTC */
> + <0 0 0 4  0 0 0 27 4>; /* INTD */
> +};

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

2015-12-22 Thread David Daney


On 12/22/2015 11:18 AM, David Daney wrote:

On 12/22/2015 02:03 AM, Will Deacon wrote:

On Mon, Dec 21, 2015 at 05:53:42PM -0800, David Daney wrote:

From: David Daney 

[...]

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index f131ba9..16ed9c3 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -172,4 +172,10 @@ config PCI_HISI
  help
Say Y here if you want PCIe controller support on HiSilicon
HIP05 SoC

+config PCIE_HOST_THUNDER_PEM
+bool "Cavium Thunder PCIe controller to off-chip devices"
+depends on PCI_HOST_GENERIC && ARM64


|| COMPILE_TEST ?

(or does the use of writeq get you? If so, maybe COMPILE_TEST && 64BIT)


Yes, we must use writeq in the driver, I will change it to
||(COMPILE_TEST && 64BIT)



Actually, it turns out that this is not easily done.

For x86, it appears difficult to include asm-generic/pci-bridge.h which 
includes the needed definition of PCI_PROBE_ONLY.  So I think it is not 
worth supporting COMPILE_TEST


David Daney


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

2015-12-22 Thread David Daney


On 12/22/2015 02:03 AM, Will Deacon wrote:

On Mon, Dec 21, 2015 at 05:53:42PM -0800, David Daney wrote:

From: David Daney 

Some Cavium ThunderX processors require quirky access methods for the
config space of the PCIe bridge.  Add a driver to provide these config
space accessor functions.  The pci-host-generic driver code is used to
configure the PCI machinery.

Signed-off-by: David Daney 
---
  .../devicetree/bindings/pci/pcie-thunder-pem.txt   |  43 
  drivers/pci/host/Kconfig   |   6 +
  drivers/pci/host/Makefile  |   1 +
  drivers/pci/host/pcie-thunder-pem.c| 283 +
  4 files changed, 333 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
  create mode 100644 drivers/pci/host/pcie-thunder-pem.c

diff --git a/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt 
b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
new file mode 100644
index 000..66824d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
@@ -0,0 +1,43 @@
+* ThunderX PEM PCIe host controller
+
+Firmware-initialized PCIe host controller found on some Cavium
+ThunderX processors.
+
+The properties and their meanings are identical to those described in
+host-heneric-pci.txt except as listed below.
+
+Properties of the host controller node that differ from
+host-heneric-pci.txt:


Consistently odd typo (s/heneric/generic/)!



I'm not sure how I managed to do that.  I will fix these and resend.


+
+- compatible : Must be "cavium,pci-host-thunder-pem"
+
+- reg: Two entries: First the configuration space for down
+   stream devices base address and size, as accessed
+   from the parent bus. Second, the register bank of
+   the PEM device PCIe bridge.
+
+Example:
+
+pem2 {
+   compatible = "cavium,pci-host-thunder-pem";
+   device_type = "pci";
+   msi-parent = <>;
+   msi-map = <0  0x1 0x1>;
+   bus-range = <0x8f 0xc7>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+
+   reg = <0x8880 0x8f00 0x0 0x3900>,  /* Configuration space */
+ <0x87e0 0xc200 0x0 0x0001>; /* PEM space */
+   ranges = <0x0100 0x00 0x0002 0x88b0 0x0002 0x00 
0x0001>, /* I/O */
+<0x0300 0x00 0x1000 0x8890 0x1000 0x0f 
0xf000>, /* mem64 */
+<0x4300 0x10 0x 0x88a0 0x 0x10 
0x>, /* mem64-pref */
+<0x0300 0x87e0 0xc2f0 0x87e0 0xc200 0x00 
0x0010>; /* mem64 PEM BAR4 */
+
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1  0 0 0 24 4>, /* INTA */
+   <0 0 0 2  0 0 0 25 4>, /* INTB */
+   <0 0 0 3  0 0 0 26 4>, /* INTC */
+   <0 0 0 4  0 0 0 27 4>; /* INTD */
+};
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index f131ba9..16ed9c3 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -172,4 +172,10 @@ config PCI_HISI
help
  Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC

+config PCIE_HOST_THUNDER_PEM
+   bool "Cavium Thunder PCIe controller to off-chip devices"
+   depends on PCI_HOST_GENERIC && ARM64


|| COMPILE_TEST ?

(or does the use of writeq get you? If so, maybe COMPILE_TEST && 64BIT)


Yes, we must use writeq in the driver, I will change it to 
||(COMPILE_TEST && 64BIT)


Thanks,
David Daney




Will



--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

2015-12-22 Thread Will Deacon

On Mon, Dec 21, 2015 at 05:53:42PM -0800, David Daney wrote:
> From: David Daney 
> 
> Some Cavium ThunderX processors require quirky access methods for the
> config space of the PCIe bridge.  Add a driver to provide these config
> space accessor functions.  The pci-host-generic driver code is used to
> configure the PCI machinery.
> 
> Signed-off-by: David Daney 
> ---
>  .../devicetree/bindings/pci/pcie-thunder-pem.txt   |  43 
>  drivers/pci/host/Kconfig   |   6 +
>  drivers/pci/host/Makefile  |   1 +
>  drivers/pci/host/pcie-thunder-pem.c| 283 
> +
>  4 files changed, 333 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
>  create mode 100644 drivers/pci/host/pcie-thunder-pem.c
> 
> diff --git a/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt 
> b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
> new file mode 100644
> index 000..66824d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
> @@ -0,0 +1,43 @@
> +* ThunderX PEM PCIe host controller
> +
> +Firmware-initialized PCIe host controller found on some Cavium
> +ThunderX processors.
> +
> +The properties and their meanings are identical to those described in
> +host-heneric-pci.txt except as listed below.
> +
> +Properties of the host controller node that differ from
> +host-heneric-pci.txt:

Consistently odd typo (s/heneric/generic/)!

> +
> +- compatible : Must be "cavium,pci-host-thunder-pem"
> +
> +- reg: Two entries: First the configuration space for down
> +   stream devices base address and size, as accessed
> +   from the parent bus. Second, the register bank of
> +   the PEM device PCIe bridge.
> +
> +Example:
> +
> +pem2 {
> + compatible = "cavium,pci-host-thunder-pem";
> + device_type = "pci";
> + msi-parent = <>;
> + msi-map = <0  0x1 0x1>;
> + bus-range = <0x8f 0xc7>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> +
> + reg = <0x8880 0x8f00 0x0 0x3900>,  /* Configuration space */
> +   <0x87e0 0xc200 0x0 0x0001>; /* PEM space */
> + ranges = <0x0100 0x00 0x0002 0x88b0 0x0002 0x00 
> 0x0001>, /* I/O */
> +  <0x0300 0x00 0x1000 0x8890 0x1000 0x0f 
> 0xf000>, /* mem64 */
> +  <0x4300 0x10 0x 0x88a0 0x 0x10 
> 0x>, /* mem64-pref */
> +  <0x0300 0x87e0 0xc2f0 0x87e0 0xc200 0x00 
> 0x0010>; /* mem64 PEM BAR4 */
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1  0 0 0 24 4>, /* INTA */
> + <0 0 0 2  0 0 0 25 4>, /* INTB */
> + <0 0 0 3  0 0 0 26 4>, /* INTC */
> + <0 0 0 4  0 0 0 27 4>; /* INTD */
> +};
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index f131ba9..16ed9c3 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -172,4 +172,10 @@ config PCI_HISI
>   help
> Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC
>  
> +config PCIE_HOST_THUNDER_PEM
> + bool "Cavium Thunder PCIe controller to off-chip devices"
> + depends on PCI_HOST_GENERIC && ARM64

|| COMPILE_TEST ?

(or does the use of writeq get you? If so, maybe COMPILE_TEST && 64BIT)

Will
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

2015-12-22 Thread David Daney


On 12/22/2015 02:03 AM, Will Deacon wrote:

On Mon, Dec 21, 2015 at 05:53:42PM -0800, David Daney wrote:

From: David Daney 

Some Cavium ThunderX processors require quirky access methods for the
config space of the PCIe bridge.  Add a driver to provide these config
space accessor functions.  The pci-host-generic driver code is used to
configure the PCI machinery.

Signed-off-by: David Daney 
---
  .../devicetree/bindings/pci/pcie-thunder-pem.txt   |  43 
  drivers/pci/host/Kconfig   |   6 +
  drivers/pci/host/Makefile  |   1 +
  drivers/pci/host/pcie-thunder-pem.c| 283 +
  4 files changed, 333 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
  create mode 100644 drivers/pci/host/pcie-thunder-pem.c

diff --git a/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt 
b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
new file mode 100644
index 000..66824d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
@@ -0,0 +1,43 @@
+* ThunderX PEM PCIe host controller
+
+Firmware-initialized PCIe host controller found on some Cavium
+ThunderX processors.
+
+The properties and their meanings are identical to those described in
+host-heneric-pci.txt except as listed below.
+
+Properties of the host controller node that differ from
+host-heneric-pci.txt:


Consistently odd typo (s/heneric/generic/)!



I'm not sure how I managed to do that.  I will fix these and resend.


+
+- compatible : Must be "cavium,pci-host-thunder-pem"
+
+- reg: Two entries: First the configuration space for down
+   stream devices base address and size, as accessed
+   from the parent bus. Second, the register bank of
+   the PEM device PCIe bridge.
+
+Example:
+
+pem2 {
+   compatible = "cavium,pci-host-thunder-pem";
+   device_type = "pci";
+   msi-parent = <>;
+   msi-map = <0  0x1 0x1>;
+   bus-range = <0x8f 0xc7>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+
+   reg = <0x8880 0x8f00 0x0 0x3900>,  /* Configuration space */
+ <0x87e0 0xc200 0x0 0x0001>; /* PEM space */
+   ranges = <0x0100 0x00 0x0002 0x88b0 0x0002 0x00 
0x0001>, /* I/O */
+<0x0300 0x00 0x1000 0x8890 0x1000 0x0f 
0xf000>, /* mem64 */
+<0x4300 0x10 0x 0x88a0 0x 0x10 
0x>, /* mem64-pref */
+<0x0300 0x87e0 0xc2f0 0x87e0 0xc200 0x00 
0x0010>; /* mem64 PEM BAR4 */
+
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1  0 0 0 24 4>, /* INTA */
+   <0 0 0 2  0 0 0 25 4>, /* INTB */
+   <0 0 0 3  0 0 0 26 4>, /* INTC */
+   <0 0 0 4  0 0 0 27 4>; /* INTD */
+};
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index f131ba9..16ed9c3 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -172,4 +172,10 @@ config PCI_HISI
help
  Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC

+config PCIE_HOST_THUNDER_PEM
+   bool "Cavium Thunder PCIe controller to off-chip devices"
+   depends on PCI_HOST_GENERIC && ARM64


|| COMPILE_TEST ?

(or does the use of writeq get you? If so, maybe COMPILE_TEST && 64BIT)


Yes, we must use writeq in the driver, I will change it to 
||(COMPILE_TEST && 64BIT)


Thanks,
David Daney




Will



--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

2015-12-22 Thread Rob Herring

On Mon, Dec 21, 2015 at 05:53:42PM -0800, David Daney wrote:
> From: David Daney 
> 
> Some Cavium ThunderX processors require quirky access methods for the
> config space of the PCIe bridge.  Add a driver to provide these config
> space accessor functions.  The pci-host-generic driver code is used to
> configure the PCI machinery.
> 
> Signed-off-by: David Daney 
> ---
>  .../devicetree/bindings/pci/pcie-thunder-pem.txt   |  43 
>  drivers/pci/host/Kconfig   |   6 +
>  drivers/pci/host/Makefile  |   1 +
>  drivers/pci/host/pcie-thunder-pem.c| 283 
> +
>  4 files changed, 333 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
>  create mode 100644 drivers/pci/host/pcie-thunder-pem.c
> 
> diff --git a/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt 
> b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
> new file mode 100644
> index 000..66824d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
> @@ -0,0 +1,43 @@
> +* ThunderX PEM PCIe host controller
> +
> +Firmware-initialized PCIe host controller found on some Cavium
> +ThunderX processors.
> +
> +The properties and their meanings are identical to those described in
> +host-heneric-pci.txt except as listed below.

s/heneric/generic/

> +
> +Properties of the host controller node that differ from
> +host-heneric-pci.txt:

ditto

> +
> +- compatible : Must be "cavium,pci-host-thunder-pem"

pcie rather than pci?


> +
> +- reg: Two entries: First the configuration space for down
> +   stream devices base address and size, as accessed
> +   from the parent bus. Second, the register bank of
> +   the PEM device PCIe bridge.
> +
> +Example:
> +
> +pem2 {

pcie-controller@...

> + compatible = "cavium,pci-host-thunder-pem";
> + device_type = "pci";
> + msi-parent = <>;
> + msi-map = <0  0x1 0x1>;
> + bus-range = <0x8f 0xc7>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> +
> + reg = <0x8880 0x8f00 0x0 0x3900>,  /* Configuration space */
> +   <0x87e0 0xc200 0x0 0x0001>; /* PEM space */
> + ranges = <0x0100 0x00 0x0002 0x88b0 0x0002 0x00 
> 0x0001>, /* I/O */
> +  <0x0300 0x00 0x1000 0x8890 0x1000 0x0f 
> 0xf000>, /* mem64 */
> +  <0x4300 0x10 0x 0x88a0 0x 0x10 
> 0x>, /* mem64-pref */
> +  <0x0300 0x87e0 0xc2f0 0x87e0 0xc200 0x00 
> 0x0010>; /* mem64 PEM BAR4 */
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1  0 0 0 24 4>, /* INTA */
> + <0 0 0 2  0 0 0 25 4>, /* INTB */
> + <0 0 0 3  0 0 0 26 4>, /* INTC */
> + <0 0 0 4  0 0 0 27 4>; /* INTD */
> +};

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

2015-12-22 Thread David Daney


On 12/22/2015 11:18 AM, David Daney wrote:

On 12/22/2015 02:03 AM, Will Deacon wrote:

On Mon, Dec 21, 2015 at 05:53:42PM -0800, David Daney wrote:

From: David Daney 

[...]

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index f131ba9..16ed9c3 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -172,4 +172,10 @@ config PCI_HISI
  help
Say Y here if you want PCIe controller support on HiSilicon
HIP05 SoC

+config PCIE_HOST_THUNDER_PEM
+bool "Cavium Thunder PCIe controller to off-chip devices"
+depends on PCI_HOST_GENERIC && ARM64


|| COMPILE_TEST ?

(or does the use of writeq get you? If so, maybe COMPILE_TEST && 64BIT)


Yes, we must use writeq in the driver, I will change it to
||(COMPILE_TEST && 64BIT)



Actually, it turns out that this is not easily done.

For x86, it appears difficult to include asm-generic/pci-bridge.h which 
includes the needed definition of PCI_PROBE_ONLY.  So I think it is not 
worth supporting COMPILE_TEST


David Daney


--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

2015-12-22 Thread Will Deacon

On Mon, Dec 21, 2015 at 05:53:42PM -0800, David Daney wrote:
> From: David Daney 
> 
> Some Cavium ThunderX processors require quirky access methods for the
> config space of the PCIe bridge.  Add a driver to provide these config
> space accessor functions.  The pci-host-generic driver code is used to
> configure the PCI machinery.
> 
> Signed-off-by: David Daney 
> ---
>  .../devicetree/bindings/pci/pcie-thunder-pem.txt   |  43 
>  drivers/pci/host/Kconfig   |   6 +
>  drivers/pci/host/Makefile  |   1 +
>  drivers/pci/host/pcie-thunder-pem.c| 283 
> +
>  4 files changed, 333 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
>  create mode 100644 drivers/pci/host/pcie-thunder-pem.c
> 
> diff --git a/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt 
> b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
> new file mode 100644
> index 000..66824d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
> @@ -0,0 +1,43 @@
> +* ThunderX PEM PCIe host controller
> +
> +Firmware-initialized PCIe host controller found on some Cavium
> +ThunderX processors.
> +
> +The properties and their meanings are identical to those described in
> +host-heneric-pci.txt except as listed below.
> +
> +Properties of the host controller node that differ from
> +host-heneric-pci.txt:

Consistently odd typo (s/heneric/generic/)!

> +
> +- compatible : Must be "cavium,pci-host-thunder-pem"
> +
> +- reg: Two entries: First the configuration space for down
> +   stream devices base address and size, as accessed
> +   from the parent bus. Second, the register bank of
> +   the PEM device PCIe bridge.
> +
> +Example:
> +
> +pem2 {
> + compatible = "cavium,pci-host-thunder-pem";
> + device_type = "pci";
> + msi-parent = <>;
> + msi-map = <0  0x1 0x1>;
> + bus-range = <0x8f 0xc7>;
> + #size-cells = <2>;
> + #address-cells = <3>;
> +
> + reg = <0x8880 0x8f00 0x0 0x3900>,  /* Configuration space */
> +   <0x87e0 0xc200 0x0 0x0001>; /* PEM space */
> + ranges = <0x0100 0x00 0x0002 0x88b0 0x0002 0x00 
> 0x0001>, /* I/O */
> +  <0x0300 0x00 0x1000 0x8890 0x1000 0x0f 
> 0xf000>, /* mem64 */
> +  <0x4300 0x10 0x 0x88a0 0x 0x10 
> 0x>, /* mem64-pref */
> +  <0x0300 0x87e0 0xc2f0 0x87e0 0xc200 0x00 
> 0x0010>; /* mem64 PEM BAR4 */
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1  0 0 0 24 4>, /* INTA */
> + <0 0 0 2  0 0 0 25 4>, /* INTB */
> + <0 0 0 3  0 0 0 26 4>, /* INTC */
> + <0 0 0 4  0 0 0 27 4>; /* INTD */
> +};
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index f131ba9..16ed9c3 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -172,4 +172,10 @@ config PCI_HISI
>   help
> Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC
>  
> +config PCIE_HOST_THUNDER_PEM
> + bool "Cavium Thunder PCIe controller to off-chip devices"
> + depends on PCI_HOST_GENERIC && ARM64

|| COMPILE_TEST ?

(or does the use of writeq get you? If so, maybe COMPILE_TEST && 64BIT)

Will
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

[PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

2015-12-21 Thread David Daney

From: David Daney 

Some Cavium ThunderX processors require quirky access methods for the
config space of the PCIe bridge.  Add a driver to provide these config
space accessor functions.  The pci-host-generic driver code is used to
configure the PCI machinery.

Signed-off-by: David Daney 
---
 .../devicetree/bindings/pci/pcie-thunder-pem.txt   |  43 
 drivers/pci/host/Kconfig   |   6 +
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-thunder-pem.c| 283 +
 4 files changed, 333 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
 create mode 100644 drivers/pci/host/pcie-thunder-pem.c

diff --git a/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt 
b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
new file mode 100644
index 000..66824d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
@@ -0,0 +1,43 @@
+* ThunderX PEM PCIe host controller
+
+Firmware-initialized PCIe host controller found on some Cavium
+ThunderX processors.
+
+The properties and their meanings are identical to those described in
+host-heneric-pci.txt except as listed below.
+
+Properties of the host controller node that differ from
+host-heneric-pci.txt:
+
+- compatible : Must be "cavium,pci-host-thunder-pem"
+
+- reg: Two entries: First the configuration space for down
+   stream devices base address and size, as accessed
+   from the parent bus. Second, the register bank of
+   the PEM device PCIe bridge.
+
+Example:
+
+pem2 {
+   compatible = "cavium,pci-host-thunder-pem";
+   device_type = "pci";
+   msi-parent = <>;
+   msi-map = <0  0x1 0x1>;
+   bus-range = <0x8f 0xc7>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+
+   reg = <0x8880 0x8f00 0x0 0x3900>,  /* Configuration space */
+ <0x87e0 0xc200 0x0 0x0001>; /* PEM space */
+   ranges = <0x0100 0x00 0x0002 0x88b0 0x0002 0x00 
0x0001>, /* I/O */
+<0x0300 0x00 0x1000 0x8890 0x1000 0x0f 
0xf000>, /* mem64 */
+<0x4300 0x10 0x 0x88a0 0x 0x10 
0x>, /* mem64-pref */
+<0x0300 0x87e0 0xc2f0 0x87e0 0xc200 0x00 
0x0010>; /* mem64 PEM BAR4 */
+
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1  0 0 0 24 4>, /* INTA */
+   <0 0 0 2  0 0 0 25 4>, /* INTB */
+   <0 0 0 3  0 0 0 26 4>, /* INTC */
+   <0 0 0 4  0 0 0 27 4>; /* INTD */
+};
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index f131ba9..16ed9c3 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -172,4 +172,10 @@ config PCI_HISI
help
  Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC
 
+config PCIE_HOST_THUNDER_PEM
+   bool "Cavium Thunder PCIe controller to off-chip devices"
+   depends on PCI_HOST_GENERIC && ARM64
+   help
+ Say Y here if you want PCIe support for CN88XX Cavium Thunder SoCs.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 9d4d3c6..70bfc37 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCIE_HOST_THUNDER_PEM) += pcie-thunder-pem.o
diff --git a/drivers/pci/host/pcie-thunder-pem.c 
b/drivers/pci/host/pcie-thunder-pem.c
new file mode 100644
index 000..3b2fa52
--- /dev/null
+++ b/drivers/pci/host/pcie-thunder-pem.c
@@ -0,0 +1,283 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ *
+ * Copyright (C) 2015 Cavium, Inc.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pci-host-generic.h"
+
+#define PEM_CFG_WR 0x28
+#define PEM_CFG_RD 0x30
+
+struct thunder_pem_pci {
+   struct gen_pci  gen_pci;
+   u32 ea_entry[3];
+   void __iomem*pem_reg_base;
+};
+
+static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn,
+  int where, int size, u32 *val)

[PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

2015-12-21 Thread David Daney

From: David Daney 

Some Cavium ThunderX processors require quirky access methods for the
config space of the PCIe bridge.  Add a driver to provide these config
space accessor functions.  The pci-host-generic driver code is used to
configure the PCI machinery.

Signed-off-by: David Daney 
---
 .../devicetree/bindings/pci/pcie-thunder-pem.txt   |  43 
 drivers/pci/host/Kconfig   |   6 +
 drivers/pci/host/Makefile  |   1 +
 drivers/pci/host/pcie-thunder-pem.c| 283 +
 4 files changed, 333 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
 create mode 100644 drivers/pci/host/pcie-thunder-pem.c

diff --git a/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt 
b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
new file mode 100644
index 000..66824d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/pcie-thunder-pem.txt
@@ -0,0 +1,43 @@
+* ThunderX PEM PCIe host controller
+
+Firmware-initialized PCIe host controller found on some Cavium
+ThunderX processors.
+
+The properties and their meanings are identical to those described in
+host-heneric-pci.txt except as listed below.
+
+Properties of the host controller node that differ from
+host-heneric-pci.txt:
+
+- compatible : Must be "cavium,pci-host-thunder-pem"
+
+- reg: Two entries: First the configuration space for down
+   stream devices base address and size, as accessed
+   from the parent bus. Second, the register bank of
+   the PEM device PCIe bridge.
+
+Example:
+
+pem2 {
+   compatible = "cavium,pci-host-thunder-pem";
+   device_type = "pci";
+   msi-parent = <>;
+   msi-map = <0  0x1 0x1>;
+   bus-range = <0x8f 0xc7>;
+   #size-cells = <2>;
+   #address-cells = <3>;
+
+   reg = <0x8880 0x8f00 0x0 0x3900>,  /* Configuration space */
+ <0x87e0 0xc200 0x0 0x0001>; /* PEM space */
+   ranges = <0x0100 0x00 0x0002 0x88b0 0x0002 0x00 
0x0001>, /* I/O */
+<0x0300 0x00 0x1000 0x8890 0x1000 0x0f 
0xf000>, /* mem64 */
+<0x4300 0x10 0x 0x88a0 0x 0x10 
0x>, /* mem64-pref */
+<0x0300 0x87e0 0xc2f0 0x87e0 0xc200 0x00 
0x0010>; /* mem64 PEM BAR4 */
+
+   #interrupt-cells = <1>;
+   interrupt-map-mask = <0 0 0 7>;
+   interrupt-map = <0 0 0 1  0 0 0 24 4>, /* INTA */
+   <0 0 0 2  0 0 0 25 4>, /* INTB */
+   <0 0 0 3  0 0 0 26 4>, /* INTC */
+   <0 0 0 4  0 0 0 27 4>; /* INTD */
+};
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index f131ba9..16ed9c3 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -172,4 +172,10 @@ config PCI_HISI
help
  Say Y here if you want PCIe controller support on HiSilicon HIP05 SoC
 
+config PCIE_HOST_THUNDER_PEM
+   bool "Cavium Thunder PCIe controller to off-chip devices"
+   depends on PCI_HOST_GENERIC && ARM64
+   help
+ Say Y here if you want PCIe support for CN88XX Cavium Thunder SoCs.
+
 endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 9d4d3c6..70bfc37 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -20,3 +20,4 @@ obj-$(CONFIG_PCIE_IPROC_BCMA) += pcie-iproc-bcma.o
 obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
 obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
+obj-$(CONFIG_PCIE_HOST_THUNDER_PEM) += pcie-thunder-pem.o
diff --git a/drivers/pci/host/pcie-thunder-pem.c 
b/drivers/pci/host/pcie-thunder-pem.c
new file mode 100644
index 000..3b2fa52
--- /dev/null
+++ b/drivers/pci/host/pcie-thunder-pem.c
@@ -0,0 +1,283 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ *
+ * Copyright (C) 2015 Cavium, Inc.
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pci-host-generic.h"
+
+#define PEM_CFG_WR 0x28
+#define PEM_CFG_RD 0x30
+
+struct thunder_pem_pci {
+   struct gen_pci  gen_pci;
+   u32 ea_entry[3];
+   void __iomem*pem_reg_base;
+};
+
+static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn,
+

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

Re: [PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

[PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

[PATCH 2/2] pci, pcie-thunder-pem: Add PCIe host driver for ThunderX processors.

10 matches

Site Navigation

Mail list logo

Footer information