Re: [PATCH 2/2] pci: dwc: add UniPhier PCIe host controller support
Hi Bjorn, On Thu, 6 Sep 2018 09:09:27 -0500 wrote: > On Thu, Sep 06, 2018 at 10:38:20AM +0900, Kunihiko Hayashi wrote: > > > > +++ b/drivers/pci/controller/dwc/pcie-uniphier.c > > > > @@ -0,0 +1,464 @@ > > > > +// SPDX-License-Identifier: GPL-2.0 > > > > +// > > > > +// PCI-express host controller driver for UniPhier SoCs > > > > +// Copyright 2018 Socionext Inc. > > > > +// Author: Kunihiko Hayashi > > > > > > Use /* ... */ comments except for the SPDX line. > > > > Okay, although I wondered which way to put, I'll replace the header next. > > The easiest thing is to look at similar files already in the tree and > follow their style. The details are here: > > https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/coding-style.rst#n540 > https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/license-rules.rst#n74 Thanks for your advice. Although I've found both styles in some sub-systems, these are helpful for me. I replaced it in posted v2. Thank you, --- Best Regards, Kunihiko Hayashi
Re: [PATCH 2/2] pci: dwc: add UniPhier PCIe host controller support
Hi Bjorn, On Thu, 6 Sep 2018 09:09:27 -0500 wrote: > On Thu, Sep 06, 2018 at 10:38:20AM +0900, Kunihiko Hayashi wrote: > > > > +++ b/drivers/pci/controller/dwc/pcie-uniphier.c > > > > @@ -0,0 +1,464 @@ > > > > +// SPDX-License-Identifier: GPL-2.0 > > > > +// > > > > +// PCI-express host controller driver for UniPhier SoCs > > > > +// Copyright 2018 Socionext Inc. > > > > +// Author: Kunihiko Hayashi > > > > > > Use /* ... */ comments except for the SPDX line. > > > > Okay, although I wondered which way to put, I'll replace the header next. > > The easiest thing is to look at similar files already in the tree and > follow their style. The details are here: > > https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/coding-style.rst#n540 > https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/license-rules.rst#n74 Thanks for your advice. Although I've found both styles in some sub-systems, these are helpful for me. I replaced it in posted v2. Thank you, --- Best Regards, Kunihiko Hayashi
Re: [PATCH 2/2] pci: dwc: add UniPhier PCIe host controller support
On Thu, Sep 06, 2018 at 10:38:20AM +0900, Kunihiko Hayashi wrote: > > > +++ b/drivers/pci/controller/dwc/pcie-uniphier.c > > > @@ -0,0 +1,464 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +// > > > +// PCI-express host controller driver for UniPhier SoCs > > > +// Copyright 2018 Socionext Inc. > > > +// Author: Kunihiko Hayashi > > > > Use /* ... */ comments except for the SPDX line. > > Okay, although I wondered which way to put, I'll replace the header next. The easiest thing is to look at similar files already in the tree and follow their style. The details are here: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/coding-style.rst#n540 https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/license-rules.rst#n74
Re: [PATCH 2/2] pci: dwc: add UniPhier PCIe host controller support
On Thu, Sep 06, 2018 at 10:38:20AM +0900, Kunihiko Hayashi wrote: > > > +++ b/drivers/pci/controller/dwc/pcie-uniphier.c > > > @@ -0,0 +1,464 @@ > > > +// SPDX-License-Identifier: GPL-2.0 > > > +// > > > +// PCI-express host controller driver for UniPhier SoCs > > > +// Copyright 2018 Socionext Inc. > > > +// Author: Kunihiko Hayashi > > > > Use /* ... */ comments except for the SPDX line. > > Okay, although I wondered which way to put, I'll replace the header next. The easiest thing is to look at similar files already in the tree and follow their style. The details are here: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/coding-style.rst#n540 https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/license-rules.rst#n74
Re: [PATCH 2/2] pci: dwc: add UniPhier PCIe host controller support
Hi Bjorn, On Wed, 5 Sep 2018 12:25:29 -0500 wrote: > Follow capitalization conventions for subject. > > On Wed, Sep 05, 2018 at 11:32:11AM +0900, Kunihiko Hayashi wrote: > > This introduces specific glue layer for UniPhier platform to support > > PCIe host controller that is based on the Designware PCIe Core, and > > this driver supports Root Complex (host) mode. > > s/Designware/DesignWare/ > s/Core/core/ I'll fix them like [1/2]. > > > diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c > > b/drivers/pci/controller/dwc/pcie-uniphier.c > > new file mode 100644 > > index 000..13ce02e > > --- /dev/null > > +++ b/drivers/pci/controller/dwc/pcie-uniphier.c > > @@ -0,0 +1,464 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// PCI-express host controller driver for UniPhier SoCs > > +// Copyright 2018 Socionext Inc. > > +// Author: Kunihiko Hayashi > > Use /* ... */ comments except for the SPDX line. Okay, although I wondered which way to put, I'll replace the header next. Thank you, --- Best Regards, Kunihiko Hayashi
Re: [PATCH 2/2] pci: dwc: add UniPhier PCIe host controller support
Hi Bjorn, On Wed, 5 Sep 2018 12:25:29 -0500 wrote: > Follow capitalization conventions for subject. > > On Wed, Sep 05, 2018 at 11:32:11AM +0900, Kunihiko Hayashi wrote: > > This introduces specific glue layer for UniPhier platform to support > > PCIe host controller that is based on the Designware PCIe Core, and > > this driver supports Root Complex (host) mode. > > s/Designware/DesignWare/ > s/Core/core/ I'll fix them like [1/2]. > > > diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c > > b/drivers/pci/controller/dwc/pcie-uniphier.c > > new file mode 100644 > > index 000..13ce02e > > --- /dev/null > > +++ b/drivers/pci/controller/dwc/pcie-uniphier.c > > @@ -0,0 +1,464 @@ > > +// SPDX-License-Identifier: GPL-2.0 > > +// > > +// PCI-express host controller driver for UniPhier SoCs > > +// Copyright 2018 Socionext Inc. > > +// Author: Kunihiko Hayashi > > Use /* ... */ comments except for the SPDX line. Okay, although I wondered which way to put, I'll replace the header next. Thank you, --- Best Regards, Kunihiko Hayashi
Re: [PATCH 2/2] pci: dwc: add UniPhier PCIe host controller support
Follow capitalization conventions for subject. On Wed, Sep 05, 2018 at 11:32:11AM +0900, Kunihiko Hayashi wrote: > This introduces specific glue layer for UniPhier platform to support > PCIe host controller that is based on the Designware PCIe Core, and > this driver supports Root Complex (host) mode. s/Designware/DesignWare/ s/Core/core/ > diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c > b/drivers/pci/controller/dwc/pcie-uniphier.c > new file mode 100644 > index 000..13ce02e > --- /dev/null > +++ b/drivers/pci/controller/dwc/pcie-uniphier.c > @@ -0,0 +1,464 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// PCI-express host controller driver for UniPhier SoCs > +// Copyright 2018 Socionext Inc. > +// Author: Kunihiko Hayashi Use /* ... */ comments except for the SPDX line.
Re: [PATCH 2/2] pci: dwc: add UniPhier PCIe host controller support
Follow capitalization conventions for subject. On Wed, Sep 05, 2018 at 11:32:11AM +0900, Kunihiko Hayashi wrote: > This introduces specific glue layer for UniPhier platform to support > PCIe host controller that is based on the Designware PCIe Core, and > this driver supports Root Complex (host) mode. s/Designware/DesignWare/ s/Core/core/ > diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c > b/drivers/pci/controller/dwc/pcie-uniphier.c > new file mode 100644 > index 000..13ce02e > --- /dev/null > +++ b/drivers/pci/controller/dwc/pcie-uniphier.c > @@ -0,0 +1,464 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// PCI-express host controller driver for UniPhier SoCs > +// Copyright 2018 Socionext Inc. > +// Author: Kunihiko Hayashi Use /* ... */ comments except for the SPDX line.
[PATCH 2/2] pci: dwc: add UniPhier PCIe host controller support
This introduces specific glue layer for UniPhier platform to support
PCIe host controller that is based on the Designware PCIe Core, and
this driver supports Root Complex (host) mode.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/Kconfig | 9 +
drivers/pci/controller/dwc/Makefile| 1 +
drivers/pci/controller/dwc/pcie-uniphier.c | 464 +
3 files changed, 474 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pcie-uniphier.c
diff --git a/drivers/pci/controller/dwc/Kconfig
b/drivers/pci/controller/dwc/Kconfig
index 91b0194..d8fdb02 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -193,4 +193,13 @@ config PCIE_HISI_STB
help
Say Y here if you want PCIe controller support on HiSilicon STB SoCs
+config PCIE_UNIPHIER
+ bool "Socionext UniPhier PCIe controllers"
+ depends on OF && (ARCH_UNIPHIER || COMPILE_TEST)
+ depends on PCI_MSI_IRQ_DOMAIN
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want PCIe controller support on UniPhier SoCs.
+ This driver supports LD20 and PXs3 SoCs.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile
b/drivers/pci/controller/dwc/Makefile
index 5d2ce72..cbde733 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
+obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c
b/drivers/pci/controller/dwc/pcie-uniphier.c
new file mode 100644
index 000..13ce02e
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-uniphier.c
@@ -0,0 +1,464 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// PCI-express host controller driver for UniPhier SoCs
+// Copyright 2018 Socionext Inc.
+// Author: Kunihiko Hayashi
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie-designware.h"
+
+#define PCL_PINCTRL0 0x002c
+#define PCL_PERST_PLDN_REGEN BIT(12)
+#define PCL_PERST_NOE_REGENBIT(11)
+#define PCL_PERST_OUT_REGENBIT(8)
+#define PCL_PERST_PLDN_REGVAL BIT(4)
+#define PCL_PERST_NOE_REGVAL BIT(3)
+#define PCL_PERST_OUT_REGVAL BIT(0)
+
+#define PCL_PIPEMON0x0044
+#define PCL_PCLK_ALIVE BIT(15)
+
+#define PCL_APP_READY_CTRL 0x8008
+#define PCL_APP_LTSSM_ENABLE BIT(0)
+
+#define PCL_APP_PM00x8078
+#define PCL_SYS_AUX_PWR_DETBIT(8)
+
+#define PCL_RCV_INT0x8108
+#define PCL_CFG_BW_MGT_ENABLE BIT(20)
+#define PCL_CFG_LINK_AUTO_BW_ENABLEBIT(19)
+#define PCL_CFG_AER_RC_ERR_MSI_ENABLE BIT(18)
+#define PCL_CFG_PME_MSI_ENABLE BIT(17)
+#define PCL_CFG_BW_MGT_STATUS BIT(4)
+#define PCL_CFG_LINK_AUTO_BW_STATUSBIT(3)
+#define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2)
+#define PCL_CFG_PME_MSI_STATUS BIT(1)
+#define PCL_RCV_INT_ALL_ENABLE \
+ (PCL_CFG_BW_MGT_ENABLE | PCL_CFG_LINK_AUTO_BW_ENABLE \
+| PCL_CFG_AER_RC_ERR_MSI_ENABLE | PCL_CFG_PME_MSI_ENABLE)
+
+#define PCL_RCV_INTX 0x810c
+#define PCL_RADM_INTD_ENABLE BIT(19)
+#define PCL_RADM_INTC_ENABLE BIT(18)
+#define PCL_RADM_INTB_ENABLE BIT(17)
+#define PCL_RADM_INTA_ENABLE BIT(16)
+#define PCL_RADM_INTD_STATUS BIT(3)
+#define PCL_RADM_INTC_STATUS BIT(2)
+#define PCL_RADM_INTB_STATUS BIT(1)
+#define PCL_RADM_INTA_STATUS BIT(0)
+#define PCL_RCV_INTX_ALL_ENABLE\
+ (PCL_RADM_INTD_ENABLE | PCL_RADM_INTC_ENABLE \
+| PCL_RADM_INTB_ENABLE | PCL_RADM_INTA_ENABLE)
+
+#define PCL_STATUS_LINK0x8140
+#define PCL_RDLH_LINK_UP BIT(1)
+#define PCL_XMLH_LINK_UP BIT(0)
+
+struct uniphier_pcie_priv {
+ void __iomem *base;
+ struct dw_pcie pci;
+ struct clk *clk;
+ struct reset_control *rst;
+ struct phy *phy;
+ struct irq_domain *irq_domain;
+};
+
+#define to_uniphier_pcie(x)dev_get_drvdata((x)->dev)
+
+static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_priv *priv)
+{
+ u32 val;
+
+ val = readl(priv->base + PCL_APP_READY_CTRL);
+ val |= PCL_APP_LTSSM_ENABLE;
+ writel(val, priv->base + PCL_APP_READY_CTRL);
+}
+
+static void uniphier_pcie_ltssm_disable(struct uniphier_pcie_priv *priv)
+{
+ u32 val;
+
+ val = readl(priv->base + PCL_APP_READY_CTRL);
+ val &=
[PATCH 2/2] pci: dwc: add UniPhier PCIe host controller support
This introduces specific glue layer for UniPhier platform to support
PCIe host controller that is based on the Designware PCIe Core, and
this driver supports Root Complex (host) mode.
Signed-off-by: Kunihiko Hayashi
---
drivers/pci/controller/dwc/Kconfig | 9 +
drivers/pci/controller/dwc/Makefile| 1 +
drivers/pci/controller/dwc/pcie-uniphier.c | 464 +
3 files changed, 474 insertions(+)
create mode 100644 drivers/pci/controller/dwc/pcie-uniphier.c
diff --git a/drivers/pci/controller/dwc/Kconfig
b/drivers/pci/controller/dwc/Kconfig
index 91b0194..d8fdb02 100644
--- a/drivers/pci/controller/dwc/Kconfig
+++ b/drivers/pci/controller/dwc/Kconfig
@@ -193,4 +193,13 @@ config PCIE_HISI_STB
help
Say Y here if you want PCIe controller support on HiSilicon STB SoCs
+config PCIE_UNIPHIER
+ bool "Socionext UniPhier PCIe controllers"
+ depends on OF && (ARCH_UNIPHIER || COMPILE_TEST)
+ depends on PCI_MSI_IRQ_DOMAIN
+ select PCIE_DW_HOST
+ help
+ Say Y here if you want PCIe controller support on UniPhier SoCs.
+ This driver supports LD20 and PXs3 SoCs.
+
endmenu
diff --git a/drivers/pci/controller/dwc/Makefile
b/drivers/pci/controller/dwc/Makefile
index 5d2ce72..cbde733 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
+obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o
# The following drivers are for devices that use the generic ACPI
# pci_root.c driver but don't support standard ECAM config access.
diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c
b/drivers/pci/controller/dwc/pcie-uniphier.c
new file mode 100644
index 000..13ce02e
--- /dev/null
+++ b/drivers/pci/controller/dwc/pcie-uniphier.c
@@ -0,0 +1,464 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// PCI-express host controller driver for UniPhier SoCs
+// Copyright 2018 Socionext Inc.
+// Author: Kunihiko Hayashi
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "pcie-designware.h"
+
+#define PCL_PINCTRL0 0x002c
+#define PCL_PERST_PLDN_REGEN BIT(12)
+#define PCL_PERST_NOE_REGENBIT(11)
+#define PCL_PERST_OUT_REGENBIT(8)
+#define PCL_PERST_PLDN_REGVAL BIT(4)
+#define PCL_PERST_NOE_REGVAL BIT(3)
+#define PCL_PERST_OUT_REGVAL BIT(0)
+
+#define PCL_PIPEMON0x0044
+#define PCL_PCLK_ALIVE BIT(15)
+
+#define PCL_APP_READY_CTRL 0x8008
+#define PCL_APP_LTSSM_ENABLE BIT(0)
+
+#define PCL_APP_PM00x8078
+#define PCL_SYS_AUX_PWR_DETBIT(8)
+
+#define PCL_RCV_INT0x8108
+#define PCL_CFG_BW_MGT_ENABLE BIT(20)
+#define PCL_CFG_LINK_AUTO_BW_ENABLEBIT(19)
+#define PCL_CFG_AER_RC_ERR_MSI_ENABLE BIT(18)
+#define PCL_CFG_PME_MSI_ENABLE BIT(17)
+#define PCL_CFG_BW_MGT_STATUS BIT(4)
+#define PCL_CFG_LINK_AUTO_BW_STATUSBIT(3)
+#define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2)
+#define PCL_CFG_PME_MSI_STATUS BIT(1)
+#define PCL_RCV_INT_ALL_ENABLE \
+ (PCL_CFG_BW_MGT_ENABLE | PCL_CFG_LINK_AUTO_BW_ENABLE \
+| PCL_CFG_AER_RC_ERR_MSI_ENABLE | PCL_CFG_PME_MSI_ENABLE)
+
+#define PCL_RCV_INTX 0x810c
+#define PCL_RADM_INTD_ENABLE BIT(19)
+#define PCL_RADM_INTC_ENABLE BIT(18)
+#define PCL_RADM_INTB_ENABLE BIT(17)
+#define PCL_RADM_INTA_ENABLE BIT(16)
+#define PCL_RADM_INTD_STATUS BIT(3)
+#define PCL_RADM_INTC_STATUS BIT(2)
+#define PCL_RADM_INTB_STATUS BIT(1)
+#define PCL_RADM_INTA_STATUS BIT(0)
+#define PCL_RCV_INTX_ALL_ENABLE\
+ (PCL_RADM_INTD_ENABLE | PCL_RADM_INTC_ENABLE \
+| PCL_RADM_INTB_ENABLE | PCL_RADM_INTA_ENABLE)
+
+#define PCL_STATUS_LINK0x8140
+#define PCL_RDLH_LINK_UP BIT(1)
+#define PCL_XMLH_LINK_UP BIT(0)
+
+struct uniphier_pcie_priv {
+ void __iomem *base;
+ struct dw_pcie pci;
+ struct clk *clk;
+ struct reset_control *rst;
+ struct phy *phy;
+ struct irq_domain *irq_domain;
+};
+
+#define to_uniphier_pcie(x)dev_get_drvdata((x)->dev)
+
+static void uniphier_pcie_ltssm_enable(struct uniphier_pcie_priv *priv)
+{
+ u32 val;
+
+ val = readl(priv->base + PCL_APP_READY_CTRL);
+ val |= PCL_APP_LTSSM_ENABLE;
+ writel(val, priv->base + PCL_APP_READY_CTRL);
+}
+
+static void uniphier_pcie_ltssm_disable(struct uniphier_pcie_priv *priv)
+{
+ u32 val;
+
+ val = readl(priv->base + PCL_APP_READY_CTRL);
+ val &=
