Re: Re: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs

[Thomas Gleixner]

On Thu, 10 Nov 2016, Bin Gao wrote:

> On Fri, Nov 11, 2016 at 12:26:40AM +0100, Thomas Gleixner wrote:
> > On Thu, 10 Nov 2016, Bin Gao wrote:
> > > > > @@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
> > > > >   }
> > > > >   }
> > > > >  
> > > > > + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> > > > 
> > > > I can understand the one below, but this one changes existing behaviour 
> > > > w/o explaining why this is correct and desired. If at all then this 
> > > > wants to be a seperate patch and not just mingled in your goldmont 
> > > > update.
> > > 
> > > native_calibrate_tsc() implements determining TSC frequency via CPUID.
> > > The purpose to add X86_FEATURE_TSC_KNOWN_FREQ flag is exactly for this 
> > > case:
> > > TSC frequency determined via CPUID or MSR are always correct and the whole
> > > calibration should be skipped.
> > 
> > Did you actually verify that this is correct and does not introduce NTP
> > issues compared to the long term calibration on such platforms?
> > 
> > We've been burnt before and myself and others wasted enough time already
> > debugging that crap.
> 
> Yes, we had a 24 hours test before on one of the CPUID capable platforms.
> With PIT calibrated frequency, we got more than 3 seconds drift whereas
> with CPUID determined frequency we only got less than 0.5 second drift.

So all that want's to be mentioned in the changelog when you add this flag
to that CPUID code path.
 
> Another fact is that on MSR capable platforms, PIT/HPET is generally not
> available so calibration won't work at all.

I know and still it want's to be documented. If you had done that in the
first place I would not ask those questions at all.

Thanks,

tglx

Re: Re: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs

[Thomas Gleixner]

On Thu, 10 Nov 2016, Bin Gao wrote:

> On Fri, Nov 11, 2016 at 12:26:40AM +0100, Thomas Gleixner wrote:
> > On Thu, 10 Nov 2016, Bin Gao wrote:
> > > > > @@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
> > > > >   }
> > > > >   }
> > > > >  
> > > > > + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> > > > 
> > > > I can understand the one below, but this one changes existing behaviour 
> > > > w/o explaining why this is correct and desired. If at all then this 
> > > > wants to be a seperate patch and not just mingled in your goldmont 
> > > > update.
> > > 
> > > native_calibrate_tsc() implements determining TSC frequency via CPUID.
> > > The purpose to add X86_FEATURE_TSC_KNOWN_FREQ flag is exactly for this 
> > > case:
> > > TSC frequency determined via CPUID or MSR are always correct and the whole
> > > calibration should be skipped.
> > 
> > Did you actually verify that this is correct and does not introduce NTP
> > issues compared to the long term calibration on such platforms?
> > 
> > We've been burnt before and myself and others wasted enough time already
> > debugging that crap.
> 
> Yes, we had a 24 hours test before on one of the CPUID capable platforms.
> With PIT calibrated frequency, we got more than 3 seconds drift whereas
> with CPUID determined frequency we only got less than 0.5 second drift.

So all that want's to be mentioned in the changelog when you add this flag
to that CPUID code path.
 
> Another fact is that on MSR capable platforms, PIT/HPET is generally not
> available so calibration won't work at all.

I know and still it want's to be documented. If you had done that in the
first place I would not ask those questions at all.

Thanks,

tglx

Re: Re: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs

[Bin Gao]

On Fri, Nov 11, 2016 at 12:26:40AM +0100, Thomas Gleixner wrote:
> On Thu, 10 Nov 2016, Bin Gao wrote:
> > > > @@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
> > > > }
> > > > }
> > > >  
> > > > +   setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> > > 
> > > I can understand the one below, but this one changes existing behaviour 
> > > w/o explaining why this is correct and desired. If at all then this wants 
> > > to be a seperate patch and not just mingled in your goldmont update.
> > 
> > native_calibrate_tsc() implements determining TSC frequency via CPUID.
> > The purpose to add X86_FEATURE_TSC_KNOWN_FREQ flag is exactly for this case:
> > TSC frequency determined via CPUID or MSR are always correct and the whole
> > calibration should be skipped.
> 
> Did you actually verify that this is correct and does not introduce NTP
> issues compared to the long term calibration on such platforms?
> 
> We've been burnt before and myself and others wasted enough time already
> debugging that crap.

Yes, we had a 24 hours test before on one of the CPUID capable platforms.
With PIT calibrated frequency, we got more than 3 seconds drift whereas
with CPUID determined frequency we only got less than 0.5 second drift.

Another fact is that on MSR capable platforms, PIT/HPET is generally not
available so calibration won't work at all.

Re: Re: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs

[Bin Gao]

On Fri, Nov 11, 2016 at 12:26:40AM +0100, Thomas Gleixner wrote:
> On Thu, 10 Nov 2016, Bin Gao wrote:
> > > > @@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
> > > > }
> > > > }
> > > >  
> > > > +   setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> > > 
> > > I can understand the one below, but this one changes existing behaviour 
> > > w/o explaining why this is correct and desired. If at all then this wants 
> > > to be a seperate patch and not just mingled in your goldmont update.
> > 
> > native_calibrate_tsc() implements determining TSC frequency via CPUID.
> > The purpose to add X86_FEATURE_TSC_KNOWN_FREQ flag is exactly for this case:
> > TSC frequency determined via CPUID or MSR are always correct and the whole
> > calibration should be skipped.
> 
> Did you actually verify that this is correct and does not introduce NTP
> issues compared to the long term calibration on such platforms?
> 
> We've been burnt before and myself and others wasted enough time already
> debugging that crap.

Yes, we had a 24 hours test before on one of the CPUID capable platforms.
With PIT calibrated frequency, we got more than 3 seconds drift whereas
with CPUID determined frequency we only got less than 0.5 second drift.

Another fact is that on MSR capable platforms, PIT/HPET is generally not
available so calibration won't work at all.

Re: Re: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs

[Thomas Gleixner]

On Thu, 10 Nov 2016, Bin Gao wrote:
> > > @@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
> > >   }
> > >   }
> > >  
> > > + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> > 
> > I can understand the one below, but this one changes existing behaviour w/o 
> > explaining why this is correct and desired. If at all then this wants to be 
> > a seperate patch and not just mingled in your goldmont update.
> 
> native_calibrate_tsc() implements determining TSC frequency via CPUID.
> The purpose to add X86_FEATURE_TSC_KNOWN_FREQ flag is exactly for this case:
> TSC frequency determined via CPUID or MSR are always correct and the whole
> calibration should be skipped.

Did you actually verify that this is correct and does not introduce NTP
issues compared to the long term calibration on such platforms?

We've been burnt before and myself and others wasted enough time already
debugging that crap.

> I will create a seperate patch for this to ensure it's not confusing with
> the MSR related change below.

Yes please.
 
> > > @@ -100,5 +100,9 @@ unsigned long cpu_khz_from_msr(void)  #ifdef 
> > > CONFIG_X86_LOCAL_APIC
> > >   lapic_timer_frequency = (freq * 1000) / HZ;  #endif
> > > +
> > > + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> > > + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> > 
> > Why is this automatically reliable and of known frequency?
> 

> As I said above, TSC frequency determined by CPUID or MSR is always considered
> "known" because it is reported by HW.
> Regarding the reliable, unfortunately however, there is no a HW way to report
> it. We were told by silicon design team it's "reliable".

Please add a comment which explains this in great length.

Thanks,

tglx

Re: Re: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs

[Thomas Gleixner]

On Thu, 10 Nov 2016, Bin Gao wrote:
> > > @@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
> > >   }
> > >   }
> > >  
> > > + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> > 
> > I can understand the one below, but this one changes existing behaviour w/o 
> > explaining why this is correct and desired. If at all then this wants to be 
> > a seperate patch and not just mingled in your goldmont update.
> 
> native_calibrate_tsc() implements determining TSC frequency via CPUID.
> The purpose to add X86_FEATURE_TSC_KNOWN_FREQ flag is exactly for this case:
> TSC frequency determined via CPUID or MSR are always correct and the whole
> calibration should be skipped.

Did you actually verify that this is correct and does not introduce NTP
issues compared to the long term calibration on such platforms?

We've been burnt before and myself and others wasted enough time already
debugging that crap.

> I will create a seperate patch for this to ensure it's not confusing with
> the MSR related change below.

Yes please.
 
> > > @@ -100,5 +100,9 @@ unsigned long cpu_khz_from_msr(void)  #ifdef 
> > > CONFIG_X86_LOCAL_APIC
> > >   lapic_timer_frequency = (freq * 1000) / HZ;  #endif
> > > +
> > > + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> > > + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> > 
> > Why is this automatically reliable and of known frequency?
> 

> As I said above, TSC frequency determined by CPUID or MSR is always considered
> "known" because it is reported by HW.
> Regarding the reliable, unfortunately however, there is no a HW way to report
> it. We were told by silicon design team it's "reliable".

Please add a comment which explains this in great length.

Thanks,

tglx

Re: Re: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs

[Bin Gao]

> > @@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
> > }
> > }
> >  
> > +   setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> 
> I can understand the one below, but this one changes existing behaviour w/o 
> explaining why this is correct and desired. If at all then this wants to be a 
> seperate patch and not just mingled in your goldmont update.

native_calibrate_tsc() implements determining TSC frequency via CPUID.
The purpose to add X86_FEATURE_TSC_KNOWN_FREQ flag is exactly for this case:
TSC frequency determined via CPUID or MSR are always correct and the whole
calibration should be skipped.

I will create a seperate patch for this to ensure it's not confusing with
the MSR related change below.

> 
> > +   /*
> > +* For Atom SoCs TSC is the only reliable clocksource.
> > +* Mark TSC reliable so no watchdog on it.
> > +*/
> > +   if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
> > +   setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> > +
> > return crystal_khz * ebx_numerator / eax_denominator;  }
> >  
> > diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c 
> > index 0fe720d..d6aa75a 100644
> > --- a/arch/x86/kernel/tsc_msr.c
> > +++ b/arch/x86/kernel/tsc_msr.c
> > @@ -100,5 +100,9 @@ unsigned long cpu_khz_from_msr(void)  #ifdef 
> > CONFIG_X86_LOCAL_APIC
> > lapic_timer_frequency = (freq * 1000) / HZ;  #endif
> > +
> > +   setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> > +   setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> 
> Why is this automatically reliable and of known frequency?

As I said above, TSC frequency determined by CPUID or MSR is always considered
"known" because it is reported by HW.
Regarding the reliable, unfortunately however, there is no a HW way to report
it. We were told by silicon design team it's "reliable".

> 
> This evades the long term TSC calibration and also disables the watchdog, 
> which might break stuff left and right.
> 
> Please makes these changes one by one and explain why they are correct on 
> their own, preferrably with some substantial backfrom from the hw folks.

Yes we confirmed with HW folks. TSC count is guaranteed to monotonically
increase at the fixed frequency even during S3/S0i3 state on these platforms.
This change will be seperate from CPUID related change in next revision.

> 
> Thanks,
> 
>   tglx
> 
> 

Re: Re: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs

[Bin Gao]

> > @@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
> > }
> > }
> >  
> > +   setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> 
> I can understand the one below, but this one changes existing behaviour w/o 
> explaining why this is correct and desired. If at all then this wants to be a 
> seperate patch and not just mingled in your goldmont update.

native_calibrate_tsc() implements determining TSC frequency via CPUID.
The purpose to add X86_FEATURE_TSC_KNOWN_FREQ flag is exactly for this case:
TSC frequency determined via CPUID or MSR are always correct and the whole
calibration should be skipped.

I will create a seperate patch for this to ensure it's not confusing with
the MSR related change below.

> 
> > +   /*
> > +* For Atom SoCs TSC is the only reliable clocksource.
> > +* Mark TSC reliable so no watchdog on it.
> > +*/
> > +   if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
> > +   setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> > +
> > return crystal_khz * ebx_numerator / eax_denominator;  }
> >  
> > diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c 
> > index 0fe720d..d6aa75a 100644
> > --- a/arch/x86/kernel/tsc_msr.c
> > +++ b/arch/x86/kernel/tsc_msr.c
> > @@ -100,5 +100,9 @@ unsigned long cpu_khz_from_msr(void)  #ifdef 
> > CONFIG_X86_LOCAL_APIC
> > lapic_timer_frequency = (freq * 1000) / HZ;  #endif
> > +
> > +   setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> > +   setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> 
> Why is this automatically reliable and of known frequency?

As I said above, TSC frequency determined by CPUID or MSR is always considered
"known" because it is reported by HW.
Regarding the reliable, unfortunately however, there is no a HW way to report
it. We were told by silicon design team it's "reliable".

> 
> This evades the long term TSC calibration and also disables the watchdog, 
> which might break stuff left and right.
> 
> Please makes these changes one by one and explain why they are correct on 
> their own, preferrably with some substantial backfrom from the hw folks.

Yes we confirmed with HW folks. TSC count is guaranteed to monotonically
increase at the fixed frequency even during S3/S0i3 state on these platforms.
This change will be seperate from CPUID related change in next revision.

> 
> Thanks,
> 
>   tglx
> 
> 

Re: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs

[Thomas Gleixner]

On Tue, 1 Nov 2016, Bin Gao wrote:
> @@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
>   }
>   }
>  
> + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);

I can understand the one below, but this one changes existing behaviour w/o
explaining why this is correct and desired. If at all then this wants to be
a seperate patch and not just mingled in your goldmont update.

> + /*
> +  * For Atom SoCs TSC is the only reliable clocksource.
> +  * Mark TSC reliable so no watchdog on it.
> +  */
> + if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
> + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> +
>   return crystal_khz * ebx_numerator / eax_denominator;
>  }
>  
> diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
> index 0fe720d..d6aa75a 100644
> --- a/arch/x86/kernel/tsc_msr.c
> +++ b/arch/x86/kernel/tsc_msr.c
> @@ -100,5 +100,9 @@ unsigned long cpu_khz_from_msr(void)
>  #ifdef CONFIG_X86_LOCAL_APIC
>   lapic_timer_frequency = (freq * 1000) / HZ;
>  #endif
> +
> + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);

Why is this automatically reliable and of known frequency?

This evades the long term TSC calibration and also disables the watchdog,
which might break stuff left and right.

Please makes these changes one by one and explain why they are correct on
their own, preferrably with some substantial backfrom from the hw folks.

Thanks,

tglx

Re: [PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs

[Thomas Gleixner]

On Tue, 1 Nov 2016, Bin Gao wrote:
> @@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
>   }
>   }
>  
> + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);

I can understand the one below, but this one changes existing behaviour w/o
explaining why this is correct and desired. If at all then this wants to be
a seperate patch and not just mingled in your goldmont update.

> + /*
> +  * For Atom SoCs TSC is the only reliable clocksource.
> +  * Mark TSC reliable so no watchdog on it.
> +  */
> + if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
> + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> +
>   return crystal_khz * ebx_numerator / eax_denominator;
>  }
>  
> diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
> index 0fe720d..d6aa75a 100644
> --- a/arch/x86/kernel/tsc_msr.c
> +++ b/arch/x86/kernel/tsc_msr.c
> @@ -100,5 +100,9 @@ unsigned long cpu_khz_from_msr(void)
>  #ifdef CONFIG_X86_LOCAL_APIC
>   lapic_timer_frequency = (freq * 1000) / HZ;
>  #endif
> +
> + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);

Why is this automatically reliable and of known frequency?

This evades the long term TSC calibration and also disables the watchdog,
which might break stuff left and right.

Please makes these changes one by one and explain why they are correct on
their own, preferrably with some substantial backfrom from the hw folks.

Thanks,

tglx

[PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs

[Bin Gao]

With X86_FEATURE_TSC_RELIABLE is split into X86_FEATURE_TSC_KNOWN_FREQ
and X86_FEATURE_TSC_KNOWN_FREQ, some platforms with reliable and
frequency-known TSC have to be marked with these new flags. These platforms
are Intel processors/SoCs supporting getting TSC frequency by MSR or CPUID.

Signed-off-by: Bin Gao 
---
 arch/x86/kernel/tsc.c   | 9 +
 arch/x86/kernel/tsc_msr.c   | 4 
 arch/x86/platform/intel-mid/mfld.c  | 5 +++--
 arch/x86/platform/intel-mid/mrfld.c | 4 ++--
 4 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index b4c82f8..4197768 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
}
}
 
+   setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
+
+   /*
+* For Atom SoCs TSC is the only reliable clocksource.
+* Mark TSC reliable so no watchdog on it.
+*/
+   if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
+   setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
+
return crystal_khz * ebx_numerator / eax_denominator;
 }
 
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 0fe720d..d6aa75a 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -100,5 +100,9 @@ unsigned long cpu_khz_from_msr(void)
 #ifdef CONFIG_X86_LOCAL_APIC
lapic_timer_frequency = (freq * 1000) / HZ;
 #endif
+
+   setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
+   setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
+
return res;
 }
diff --git a/arch/x86/platform/intel-mid/mfld.c 
b/arch/x86/platform/intel-mid/mfld.c
index 1eb47b6..3fa41b4 100644
--- a/arch/x86/platform/intel-mid/mfld.c
+++ b/arch/x86/platform/intel-mid/mfld.c
@@ -49,8 +49,9 @@ static unsigned long __init mfld_calibrate_tsc(void)
fast_calibrate = ratio * fsb;
pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
lapic_timer_frequency = fsb * 1000 / HZ;
-   /* mark tsc clocksource as reliable */
-   set_cpu_cap(_cpu_data, X86_FEATURE_TSC_RELIABLE);
+
+   setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
+   setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
 
return fast_calibrate;
 }
diff --git a/arch/x86/platform/intel-mid/mrfld.c 
b/arch/x86/platform/intel-mid/mrfld.c
index 59253db..9477b7e 100644
--- a/arch/x86/platform/intel-mid/mrfld.c
+++ b/arch/x86/platform/intel-mid/mrfld.c
@@ -78,8 +78,8 @@ static unsigned long __init tangier_calibrate_tsc(void)
pr_debug("Setting lapic_timer_frequency = %d\n",
lapic_timer_frequency);
 
-   /* mark tsc clocksource as reliable */
-   set_cpu_cap(_cpu_data, X86_FEATURE_TSC_RELIABLE);
+   setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
+   setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
 
return fast_calibrate;
 }
-- 
1.9.1

[PATCH 2/2] x86: use KNOWN_FREQ and RELIABLE TSC flags on certain processors/SoCs

[Bin Gao]

With X86_FEATURE_TSC_RELIABLE is split into X86_FEATURE_TSC_KNOWN_FREQ
and X86_FEATURE_TSC_KNOWN_FREQ, some platforms with reliable and
frequency-known TSC have to be marked with these new flags. These platforms
are Intel processors/SoCs supporting getting TSC frequency by MSR or CPUID.

Signed-off-by: Bin Gao 
---
 arch/x86/kernel/tsc.c   | 9 +
 arch/x86/kernel/tsc_msr.c   | 4 
 arch/x86/platform/intel-mid/mfld.c  | 5 +++--
 arch/x86/platform/intel-mid/mrfld.c | 4 ++--
 4 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index b4c82f8..4197768 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
}
}
 
+   setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
+
+   /*
+* For Atom SoCs TSC is the only reliable clocksource.
+* Mark TSC reliable so no watchdog on it.
+*/
+   if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
+   setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
+
return crystal_khz * ebx_numerator / eax_denominator;
 }
 
diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index 0fe720d..d6aa75a 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -100,5 +100,9 @@ unsigned long cpu_khz_from_msr(void)
 #ifdef CONFIG_X86_LOCAL_APIC
lapic_timer_frequency = (freq * 1000) / HZ;
 #endif
+
+   setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
+   setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
+
return res;
 }
diff --git a/arch/x86/platform/intel-mid/mfld.c 
b/arch/x86/platform/intel-mid/mfld.c
index 1eb47b6..3fa41b4 100644
--- a/arch/x86/platform/intel-mid/mfld.c
+++ b/arch/x86/platform/intel-mid/mfld.c
@@ -49,8 +49,9 @@ static unsigned long __init mfld_calibrate_tsc(void)
fast_calibrate = ratio * fsb;
pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
lapic_timer_frequency = fsb * 1000 / HZ;
-   /* mark tsc clocksource as reliable */
-   set_cpu_cap(_cpu_data, X86_FEATURE_TSC_RELIABLE);
+
+   setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
+   setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
 
return fast_calibrate;
 }
diff --git a/arch/x86/platform/intel-mid/mrfld.c 
b/arch/x86/platform/intel-mid/mrfld.c
index 59253db..9477b7e 100644
--- a/arch/x86/platform/intel-mid/mrfld.c
+++ b/arch/x86/platform/intel-mid/mrfld.c
@@ -78,8 +78,8 @@ static unsigned long __init tangier_calibrate_tsc(void)
pr_debug("Setting lapic_timer_frequency = %d\n",
lapic_timer_frequency);
 
-   /* mark tsc clocksource as reliable */
-   set_cpu_cap(_cpu_data, X86_FEATURE_TSC_RELIABLE);
+   setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
+   setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
 
return fast_calibrate;
 }
-- 
1.9.1