[PATCH 2/8] serial: tegra: Add delay after enabling FIFO mode
For all tegra devices (up to t210), there is a hardware issue that requires software to wait for 3 UART clock periods after enabling the TX fifo, otherwise data could be lost. Signed-off-by: Jon Hunter --- drivers/tty/serial/serial-tegra.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c index 9e08d3f07509..0d9d7ceb1dbb 100644 --- a/drivers/tty/serial/serial-tegra.c +++ b/drivers/tty/serial/serial-tegra.c @@ -885,6 +885,16 @@ static int tegra_uart_hw_init(struct tegra_uart_port *tup) tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); + /* Dummy read to ensure the write is posted */ + tegra_uart_read(tup, UART_SCR); + + /* +* For all tegra devices (up to t210), there is a hardware issue that +* requires software to wait for 3 UART clock periods after enabling +* the TX fifo, otherwise data could be lost. +*/ + tegra_uart_wait_cycle_time(tup, 3); + /* * Initialize the UART with default configuration * (115200, N, 8, 1) so that the receive DMA buffer may be -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 2/8] serial: tegra: Add delay after enabling FIFO mode
For all tegra devices (up to t210), there is a hardware issue that requires software to wait for 3 UART clock periods after enabling the TX fifo, otherwise data could be lost. Signed-off-by: Jon Hunter jonath...@nvidia.com --- drivers/tty/serial/serial-tegra.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c index 9e08d3f07509..0d9d7ceb1dbb 100644 --- a/drivers/tty/serial/serial-tegra.c +++ b/drivers/tty/serial/serial-tegra.c @@ -885,6 +885,16 @@ static int tegra_uart_hw_init(struct tegra_uart_port *tup) tup-fcr_shadow |= TEGRA_UART_TX_TRIG_16B; tegra_uart_write(tup, tup-fcr_shadow, UART_FCR); + /* Dummy read to ensure the write is posted */ + tegra_uart_read(tup, UART_SCR); + + /* +* For all tegra devices (up to t210), there is a hardware issue that +* requires software to wait for 3 UART clock periods after enabling +* the TX fifo, otherwise data could be lost. +*/ + tegra_uart_wait_cycle_time(tup, 3); + /* * Initialize the UART with default configuration * (115200, N, 8, 1) so that the receive DMA buffer may be -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
