Re: [PATCH 2/9] ARM: at91/dt: add ethernet phy to at91rm9200ek board

2013-11-18 Thread boris brezillon

On 28/08/2013 13:03, Boris BREZILLON wrote:

Add ethernet phy node in at91rm9200ek.dts.
The reg register is not specified, as it may differ depending on the init
process of the board:
ADDR0/1 phy pins are connected to PA13/14 rm9200 pins. Which means the phy
will take its address from these pins during the reset process.

The macb driver will launch a full scan on the mdio bus to discover the phy
address.

Signed-off-by: Boris BREZILLON 
---
  arch/arm/boot/dts/at91rm9200ek.dts |5 +
  1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/at91rm9200ek.dts 
b/arch/arm/boot/dts/at91rm9200ek.dts
index d2d72c3..37b0880 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -47,6 +47,11 @@
macb0: ethernet@fffbc000 {
phy-mode = "rmii";
status = "okay";
+
+   phy0: ethernet-phy {
+   interrupt-parent = <>;
+   interrupts = <4 IRQ_TYPE_EDGE_FALLING>;


rm9200 pio controller does not support specific edge detection.
The line above should be replaced with:
interrupts = <4 IRQ_TYPE_EDGE_BOTH>;
or
interrupts = <4 0>;

Nicolas, I know you were planning to push this patch for 3.14.
If you haven't done it yet (or if you changed your mind), I can send a 
new version including this fix.




+   };
};

usb1: gadget@fffb {



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Re: [PATCH 2/9] ARM: at91/dt: add ethernet phy to at91rm9200ek board

2013-11-18 Thread boris brezillon

On 28/08/2013 13:03, Boris BREZILLON wrote:

Add ethernet phy node in at91rm9200ek.dts.
The reg register is not specified, as it may differ depending on the init
process of the board:
ADDR0/1 phy pins are connected to PA13/14 rm9200 pins. Which means the phy
will take its address from these pins during the reset process.

The macb driver will launch a full scan on the mdio bus to discover the phy
address.

Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
  arch/arm/boot/dts/at91rm9200ek.dts |5 +
  1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/at91rm9200ek.dts 
b/arch/arm/boot/dts/at91rm9200ek.dts
index d2d72c3..37b0880 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -47,6 +47,11 @@
macb0: ethernet@fffbc000 {
phy-mode = rmii;
status = okay;
+
+   phy0: ethernet-phy {
+   interrupt-parent = pioC;
+   interrupts = 4 IRQ_TYPE_EDGE_FALLING;


rm9200 pio controller does not support specific edge detection.
The line above should be replaced with:
interrupts = 4 IRQ_TYPE_EDGE_BOTH;
or
interrupts = 4 0;

Nicolas, I know you were planning to push this patch for 3.14.
If you haven't done it yet (or if you changed your mind), I can send a 
new version including this fix.




+   };
};

usb1: gadget@fffb {



--
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the body of a message to majord...@vger.kernel.org
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[PATCH 2/9] ARM: at91/dt: add ethernet phy to at91rm9200ek board

2013-08-28 Thread Boris BREZILLON
Add ethernet phy node in at91rm9200ek.dts.
The reg register is not specified, as it may differ depending on the init
process of the board:
ADDR0/1 phy pins are connected to PA13/14 rm9200 pins. Which means the phy
will take its address from these pins during the reset process.

The macb driver will launch a full scan on the mdio bus to discover the phy
address.

Signed-off-by: Boris BREZILLON 
---
 arch/arm/boot/dts/at91rm9200ek.dts |5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/at91rm9200ek.dts 
b/arch/arm/boot/dts/at91rm9200ek.dts
index d2d72c3..37b0880 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -47,6 +47,11 @@
macb0: ethernet@fffbc000 {
phy-mode = "rmii";
status = "okay";
+
+   phy0: ethernet-phy {
+   interrupt-parent = <>;
+   interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+   };
};
 
usb1: gadget@fffb {
-- 
1.7.9.5

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Please read the FAQ at  http://www.tux.org/lkml/


[PATCH 2/9] ARM: at91/dt: add ethernet phy to at91rm9200ek board

2013-08-28 Thread Boris BREZILLON
Add ethernet phy node in at91rm9200ek.dts.
The reg register is not specified, as it may differ depending on the init
process of the board:
ADDR0/1 phy pins are connected to PA13/14 rm9200 pins. Which means the phy
will take its address from these pins during the reset process.

The macb driver will launch a full scan on the mdio bus to discover the phy
address.

Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
 arch/arm/boot/dts/at91rm9200ek.dts |5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boot/dts/at91rm9200ek.dts 
b/arch/arm/boot/dts/at91rm9200ek.dts
index d2d72c3..37b0880 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -47,6 +47,11 @@
macb0: ethernet@fffbc000 {
phy-mode = rmii;
status = okay;
+
+   phy0: ethernet-phy {
+   interrupt-parent = pioC;
+   interrupts = 4 IRQ_TYPE_EDGE_FALLING;
+   };
};
 
usb1: gadget@fffb {
-- 
1.7.9.5

--
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the body of a message to majord...@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/