Re: [PATCH 20/30] x86, mm: remove hard-coded ASID limit checks

[Thomas Gleixner]

On Fri, 10 Nov 2017, Dave Hansen wrote:
>  
> +/* There are 12 bits of space for ASIDS in CR3 */
> +#define CR3_HW_ASID_BITS 12
> +/* When enabled, KAISER consumes a single bit for user/kernel switches */
> +#define KAISER_CONSUMED_ASID_BITS 0
> +
> +#define CR3_AVAIL_ASID_BITS (CR3_HW_ASID_BITS-KAISER_CONSUMED_ASID_BITS)

Spaces around '-' please. Same for other operators.

> +/*
> + * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid.  -1 below
> + * to account for them being zero-absed.  Another -1 is because ASID 0

s/absed/based/

> + * is reserved for use by non-PCID-aware users.
> + */
> +#define MAX_ASID_AVAILABLE ((1< +
>  /*

Thanks,

tglx

Re: [PATCH 20/30] x86, mm: remove hard-coded ASID limit checks

[Thomas Gleixner]

On Fri, 10 Nov 2017, Dave Hansen wrote:
>  
> +/* There are 12 bits of space for ASIDS in CR3 */
> +#define CR3_HW_ASID_BITS 12
> +/* When enabled, KAISER consumes a single bit for user/kernel switches */
> +#define KAISER_CONSUMED_ASID_BITS 0
> +
> +#define CR3_AVAIL_ASID_BITS (CR3_HW_ASID_BITS-KAISER_CONSUMED_ASID_BITS)

Spaces around '-' please. Same for other operators.

> +/*
> + * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid.  -1 below
> + * to account for them being zero-absed.  Another -1 is because ASID 0

s/absed/based/

> + * is reserved for use by non-PCID-aware users.
> + */
> +#define MAX_ASID_AVAILABLE ((1< +
>  /*

Thanks,

tglx

[PATCH 20/30] x86, mm: remove hard-coded ASID limit checks

[Dave Hansen]

From: Dave Hansen 

First, it's nice to remove the magic numbers.

Second, KAISER is going to consume half of the available ASID
space.  The space is currently unused, but add a comment to spell
out this new restriction.

Signed-off-by: Dave Hansen 
Cc: Moritz Lipp 
Cc: Daniel Gruss 
Cc: Michael Schwarz 
Cc: Richard Fellner 
Cc: Andy Lutomirski 
Cc: Linus Torvalds 
Cc: Kees Cook 
Cc: Hugh Dickins 
Cc: x...@kernel.org
---

 b/arch/x86/include/asm/tlbflush.h |   17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff -puN arch/x86/include/asm/tlbflush.h~kaiser-pcid-pre-build-asids-macros 
arch/x86/include/asm/tlbflush.h
--- a/arch/x86/include/asm/tlbflush.h~kaiser-pcid-pre-build-asids-macros
2017-11-10 11:22:15.990244932 -0800
+++ b/arch/x86/include/asm/tlbflush.h   2017-11-10 11:22:15.994244932 -0800
@@ -74,6 +74,19 @@ static inline u64 inc_mm_tlb_gen(struct
return new_tlb_gen;
 }
 
+/* There are 12 bits of space for ASIDS in CR3 */
+#define CR3_HW_ASID_BITS 12
+/* When enabled, KAISER consumes a single bit for user/kernel switches */
+#define KAISER_CONSUMED_ASID_BITS 0
+
+#define CR3_AVAIL_ASID_BITS (CR3_HW_ASID_BITS-KAISER_CONSUMED_ASID_BITS)
+/*
+ * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid.  -1 below
+ * to account for them being zero-absed.  Another -1 is because ASID 0
+ * is reserved for use by non-PCID-aware users.
+ */
+#define MAX_ASID_AVAILABLE ((1< 4094);
+   VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
return __sme_pa(pgd) | (asid + 1);
} else {
VM_WARN_ON_ONCE(asid != 0);
@@ -97,7 +110,7 @@ static inline unsigned long build_cr3(pg
 
 static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
 {
-   VM_WARN_ON_ONCE(asid > 4094);
+   VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
return __sme_pa(pgd) | (asid + 1) | CR3_NOFLUSH;
 }
 
_

[PATCH 20/30] x86, mm: remove hard-coded ASID limit checks

[Dave Hansen]

From: Dave Hansen 

First, it's nice to remove the magic numbers.

Second, KAISER is going to consume half of the available ASID
space.  The space is currently unused, but add a comment to spell
out this new restriction.

Signed-off-by: Dave Hansen 
Cc: Moritz Lipp 
Cc: Daniel Gruss 
Cc: Michael Schwarz 
Cc: Richard Fellner 
Cc: Andy Lutomirski 
Cc: Linus Torvalds 
Cc: Kees Cook 
Cc: Hugh Dickins 
Cc: x...@kernel.org
---

 b/arch/x86/include/asm/tlbflush.h |   17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff -puN arch/x86/include/asm/tlbflush.h~kaiser-pcid-pre-build-asids-macros 
arch/x86/include/asm/tlbflush.h
--- a/arch/x86/include/asm/tlbflush.h~kaiser-pcid-pre-build-asids-macros
2017-11-10 11:22:15.990244932 -0800
+++ b/arch/x86/include/asm/tlbflush.h   2017-11-10 11:22:15.994244932 -0800
@@ -74,6 +74,19 @@ static inline u64 inc_mm_tlb_gen(struct
return new_tlb_gen;
 }
 
+/* There are 12 bits of space for ASIDS in CR3 */
+#define CR3_HW_ASID_BITS 12
+/* When enabled, KAISER consumes a single bit for user/kernel switches */
+#define KAISER_CONSUMED_ASID_BITS 0
+
+#define CR3_AVAIL_ASID_BITS (CR3_HW_ASID_BITS-KAISER_CONSUMED_ASID_BITS)
+/*
+ * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid.  -1 below
+ * to account for them being zero-absed.  Another -1 is because ASID 0
+ * is reserved for use by non-PCID-aware users.
+ */
+#define MAX_ASID_AVAILABLE ((1< 4094);
+   VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
return __sme_pa(pgd) | (asid + 1);
} else {
VM_WARN_ON_ONCE(asid != 0);
@@ -97,7 +110,7 @@ static inline unsigned long build_cr3(pg
 
 static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
 {
-   VM_WARN_ON_ONCE(asid > 4094);
+   VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
return __sme_pa(pgd) | (asid + 1) | CR3_NOFLUSH;
 }
 
_

Re: [PATCH 20/30] x86, mm: remove hard-coded ASID limit checks

[Dave Hansen]

On 11/10/2017 04:20 AM, Peter Zijlstra wrote:
> On Wed, Nov 08, 2017 at 11:47:24AM -0800, Dave Hansen wrote:
>> +#define CR3_HW_ASID_BITS 12
>> +#define NR_AVAIL_ASIDS ((1< That evaluates to 4095
> 
>> -VM_WARN_ON_ONCE(asid > 4094);
>> +VM_WARN_ON_ONCE(asid > NR_AVAIL_ASIDS);
> Not the same number

I think this got fixed up in the next patch (the check becomes a >=),
but I'll fix this to make it more clean and fix the intermediate breakage.

Re: [PATCH 20/30] x86, mm: remove hard-coded ASID limit checks

[Dave Hansen]

On 11/10/2017 04:20 AM, Peter Zijlstra wrote:
> On Wed, Nov 08, 2017 at 11:47:24AM -0800, Dave Hansen wrote:
>> +#define CR3_HW_ASID_BITS 12
>> +#define NR_AVAIL_ASIDS ((1< That evaluates to 4095
> 
>> -VM_WARN_ON_ONCE(asid > 4094);
>> +VM_WARN_ON_ONCE(asid > NR_AVAIL_ASIDS);
> Not the same number

I think this got fixed up in the next patch (the check becomes a >=),
but I'll fix this to make it more clean and fix the intermediate breakage.

Re: [PATCH 20/30] x86, mm: remove hard-coded ASID limit checks

[Peter Zijlstra]

On Wed, Nov 08, 2017 at 11:47:24AM -0800, Dave Hansen wrote:
> +#define CR3_HW_ASID_BITS 12
> +#define NR_AVAIL_ASIDS ((1< - VM_WARN_ON_ONCE(asid > 4094);
> + VM_WARN_ON_ONCE(asid > NR_AVAIL_ASIDS);

Not the same number

Re: [PATCH 20/30] x86, mm: remove hard-coded ASID limit checks

[Peter Zijlstra]

On Wed, Nov 08, 2017 at 11:47:24AM -0800, Dave Hansen wrote:
> +#define CR3_HW_ASID_BITS 12
> +#define NR_AVAIL_ASIDS ((1< - VM_WARN_ON_ONCE(asid > 4094);
> + VM_WARN_ON_ONCE(asid > NR_AVAIL_ASIDS);

Not the same number

[PATCH 20/30] x86, mm: remove hard-coded ASID limit checks

[Dave Hansen]

From: Dave Hansen 

First, it's nice to remove the magic numbers.

Second, KAISER is going to eat up half of the available ASID
space.  We do not use it today, but we need to at least spell
out this new restriction.

Signed-off-by: Dave Hansen 
Cc: Moritz Lipp 
Cc: Daniel Gruss 
Cc: Michael Schwarz 
Cc: Richard Fellner 
Cc: Andy Lutomirski 
Cc: Linus Torvalds 
Cc: Kees Cook 
Cc: Hugh Dickins 
Cc: x...@kernel.org
---

 b/arch/x86/include/asm/tlbflush.h |   16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff -puN arch/x86/include/asm/tlbflush.h~kaiser-pcid-pre-build-asids-macros 
arch/x86/include/asm/tlbflush.h
--- a/arch/x86/include/asm/tlbflush.h~kaiser-pcid-pre-build-asids-macros
2017-11-08 10:45:36.780681376 -0800
+++ b/arch/x86/include/asm/tlbflush.h   2017-11-08 10:45:36.784681376 -0800
@@ -74,6 +74,18 @@ static inline u64 inc_mm_tlb_gen(struct
return new_tlb_gen;
 }
 
+/* There are 12 bits of space for ASIDS in CR3 */
+#define CR3_HW_ASID_BITS 12
+/* When enabled, KAISER consumes a single bit for user/kernel switches */
+#define KAISER_CONSUMED_ASID_BITS 0
+
+#define CR3_AVAIL_ASID_BITS (CR3_HW_ASID_BITS-KAISER_CONSUMED_ASID_BITS)
+/*
+ * We lose a single extra ASID because 0 is reserved for use
+ * by non-PCID-aware users.
+ */
+#define NR_AVAIL_ASIDS ((1< 4094);
+   VM_WARN_ON_ONCE(asid > NR_AVAIL_ASIDS);
return __sme_pa(pgd) | (asid + 1);
} else {
VM_WARN_ON_ONCE(asid != 0);
@@ -97,7 +109,7 @@ static inline unsigned long build_cr3(pg
 
 static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
 {
-   VM_WARN_ON_ONCE(asid > 4094);
+   VM_WARN_ON_ONCE(asid > NR_AVAIL_ASIDS);
return __sme_pa(pgd) | (asid + 1) | CR3_NOFLUSH;
 }
 
_

[PATCH 20/30] x86, mm: remove hard-coded ASID limit checks

[Dave Hansen]

From: Dave Hansen 

First, it's nice to remove the magic numbers.

Second, KAISER is going to eat up half of the available ASID
space.  We do not use it today, but we need to at least spell
out this new restriction.

Signed-off-by: Dave Hansen 
Cc: Moritz Lipp 
Cc: Daniel Gruss 
Cc: Michael Schwarz 
Cc: Richard Fellner 
Cc: Andy Lutomirski 
Cc: Linus Torvalds 
Cc: Kees Cook 
Cc: Hugh Dickins 
Cc: x...@kernel.org
---

 b/arch/x86/include/asm/tlbflush.h |   16 ++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff -puN arch/x86/include/asm/tlbflush.h~kaiser-pcid-pre-build-asids-macros 
arch/x86/include/asm/tlbflush.h
--- a/arch/x86/include/asm/tlbflush.h~kaiser-pcid-pre-build-asids-macros
2017-11-08 10:45:36.780681376 -0800
+++ b/arch/x86/include/asm/tlbflush.h   2017-11-08 10:45:36.784681376 -0800
@@ -74,6 +74,18 @@ static inline u64 inc_mm_tlb_gen(struct
return new_tlb_gen;
 }
 
+/* There are 12 bits of space for ASIDS in CR3 */
+#define CR3_HW_ASID_BITS 12
+/* When enabled, KAISER consumes a single bit for user/kernel switches */
+#define KAISER_CONSUMED_ASID_BITS 0
+
+#define CR3_AVAIL_ASID_BITS (CR3_HW_ASID_BITS-KAISER_CONSUMED_ASID_BITS)
+/*
+ * We lose a single extra ASID because 0 is reserved for use
+ * by non-PCID-aware users.
+ */
+#define NR_AVAIL_ASIDS ((1< 4094);
+   VM_WARN_ON_ONCE(asid > NR_AVAIL_ASIDS);
return __sme_pa(pgd) | (asid + 1);
} else {
VM_WARN_ON_ONCE(asid != 0);
@@ -97,7 +109,7 @@ static inline unsigned long build_cr3(pg
 
 static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
 {
-   VM_WARN_ON_ONCE(asid > 4094);
+   VM_WARN_ON_ONCE(asid > NR_AVAIL_ASIDS);
return __sme_pa(pgd) | (asid + 1) | CR3_NOFLUSH;
 }
 
_