Re: [PATCH 20/31] nds32: L2 cache support

[Greentime Hu]

2017-11-08 17:48 GMT+08:00 Arnd Bergmann :
> On Wed, Nov 8, 2017 at 6:55 AM, Greentime Hu  wrote:
>> From: Greentime Hu 
>>
>> Signed-off-by: Vincent Chen 
>> Signed-off-by: Greentime Hu 
>
>> +
>> +/* This is defined for head.S to use due to device tree is not yet built. */
>> +#define L2CC_PA_BASE   0x90F0
>
> This looks problematic, since it prevents you from using the same head.S for
> multiple SoCs that have different L2 controllers or that have them at 
> different
> addresses.
>
> What does head.S actually do to the L2CC? Could the boot protocol require
> that to be done by the boot loader before entering the kernel instead?
>

Thanks.
It will disable and invalidate L2 cache. I think we can do these
things in bootloader.
I will refine it in the next version patch.

Re: [PATCH 20/31] nds32: L2 cache support

[Greentime Hu]

2017-11-08 17:48 GMT+08:00 Arnd Bergmann :
> On Wed, Nov 8, 2017 at 6:55 AM, Greentime Hu  wrote:
>> From: Greentime Hu 
>>
>> Signed-off-by: Vincent Chen 
>> Signed-off-by: Greentime Hu 
>
>> +
>> +/* This is defined for head.S to use due to device tree is not yet built. */
>> +#define L2CC_PA_BASE   0x90F0
>
> This looks problematic, since it prevents you from using the same head.S for
> multiple SoCs that have different L2 controllers or that have them at 
> different
> addresses.
>
> What does head.S actually do to the L2CC? Could the boot protocol require
> that to be done by the boot loader before entering the kernel instead?
>

Thanks.
It will disable and invalidate L2 cache. I think we can do these
things in bootloader.
I will refine it in the next version patch.

Re: [PATCH 20/31] nds32: L2 cache support

[Arnd Bergmann]

On Wed, Nov 8, 2017 at 6:55 AM, Greentime Hu  wrote:
> From: Greentime Hu 
>
> Signed-off-by: Vincent Chen 
> Signed-off-by: Greentime Hu 

> +
> +/* This is defined for head.S to use due to device tree is not yet built. */
> +#define L2CC_PA_BASE   0x90F0

This looks problematic, since it prevents you from using the same head.S for
multiple SoCs that have different L2 controllers or that have them at different
addresses.

What does head.S actually do to the L2CC? Could the boot protocol require
that to be done by the boot loader before entering the kernel instead?

 Arnd

Re: [PATCH 20/31] nds32: L2 cache support

[Arnd Bergmann]

On Wed, Nov 8, 2017 at 6:55 AM, Greentime Hu  wrote:
> From: Greentime Hu 
>
> Signed-off-by: Vincent Chen 
> Signed-off-by: Greentime Hu 

> +
> +/* This is defined for head.S to use due to device tree is not yet built. */
> +#define L2CC_PA_BASE   0x90F0

This looks problematic, since it prevents you from using the same head.S for
multiple SoCs that have different L2 controllers or that have them at different
addresses.

What does head.S actually do to the L2CC? Could the boot protocol require
that to be done by the boot loader before entering the kernel instead?

 Arnd

[PATCH 20/31] nds32: L2 cache support

[Greentime Hu]

From: Greentime Hu 

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/l2_cache.h |  158 +
 arch/nds32/kernel/atl2c.c |   77 ++
 2 files changed, 235 insertions(+)
 create mode 100644 arch/nds32/include/asm/l2_cache.h
 create mode 100644 arch/nds32/kernel/atl2c.c

diff --git a/arch/nds32/include/asm/l2_cache.h 
b/arch/nds32/include/asm/l2_cache.h
new file mode 100644
index 000..b8530bd
--- /dev/null
+++ b/arch/nds32/include/asm/l2_cache.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#ifndef L2_CACHE_H
+#define L2_CACHE_H
+
+/* This is defined for head.S to use due to device tree is not yet built. */
+#define L2CC_PA_BASE   0x90F0
+
+/* CCTL_CMD_OP */
+#define L2_CA_CONF_OFF 0x0
+#defineL2_IF_CONF_OFF  0x4
+#define L2CC_SETUP_OFF 0x8
+#define L2CC_PROT_OFF  0xC
+#define L2CC_CTRL_OFF  0x10
+#define L2_INT_EN_OFF   0x20
+#define L2_STA_OFF  0x24
+#define RDERR_ADDR_OFF 0x28
+#define WRERR_ADDR_OFF 0x2c
+#define EVDPTERR_ADDR_OFF  0x30
+#define IMPL3ERR_ADDR_OFF  0x34
+#define L2_CNT0_CTRL_OFF0x40
+#define L2_EVNT_CNT0_OFF0x44
+#define L2_CNT1_CTRL_OFF0x48
+#define L2_EVNT_CNT1_OFF0x4c
+#define L2_CCTL_CMD_OFF0x60
+#define L2_CCTL_STATUS_OFF 0x64
+#define L2_LINE_TAG_OFF0x68
+#define L2_LINE_DPT_OFF0x70
+
+#define CCTL_CMD_L2_IX_INVAL0x0
+#define CCTL_CMD_L2_PA_INVAL0x1
+#define CCTL_CMD_L2_IX_WB   0x2
+#define CCTL_CMD_L2_PA_WB   0x3
+#define CCTL_CMD_L2_PA_WBINVAL  0x5
+#define CCTL_CMD_L2_SYNC0xa
+
+/* CCTL_CMD_TYPE */
+#define CCTL_SINGLE_CMD 0
+#define CCTL_BLOCK_CMD  0x10
+#define CCTL_ALL_CMD   0x10
+
+/**
+ * L2_CA_CONF (Cache architecture configuration)
+ */
+#define L2_CA_CONF_offL2SET0
+#define L2_CA_CONF_offL2WAY4
+#define L2_CA_CONF_offL2CLSZ8
+#define L2_CA_CONF_offL2DW 11
+#define L2_CA_CONF_offL2PT 14
+#define L2_CA_CONF_offL2VER16
+
+#define L2_CA_CONF_mskL2SET(0xFUL << L2_CA_CONF_offL2SET)
+#define L2_CA_CONF_mskL2WAY(0xFUL << L2_CA_CONF_offL2WAY)
+#define L2_CA_CONF_mskL2CLSZ(0x7UL << L2_CA_CONF_offL2CLSZ)
+#define L2_CA_CONF_mskL2DW (0x7UL << L2_CA_CONF_offL2DW)
+#define L2_CA_CONF_mskL2PT (0x3UL << L2_CA_CONF_offL2PT)
+#define L2_CA_CONF_mskL2VER(0xUL << L2_CA_CONF_offL2VER)
+
+/**
+ * L2CC_SETUP (L2CC Setup register)
+ */
+#define L2CC_SETUP_offPART  0
+#define L2CC_SETUP_mskPART  (0x3UL << L2CC_SETUP_offPART)
+#define L2CC_SETUP_offDDLATC4
+#define L2CC_SETUP_mskDDLATC(0x3UL << L2CC_SETUP_offDDLATC)
+#define L2CC_SETUP_offTDLATC8
+#define L2CC_SETUP_mskTDLATC(0x3UL << L2CC_SETUP_offTDLATC)
+
+/**
+ * L2CC_PROT (L2CC Protect register)
+ */
+#define L2CC_PROT_offMRWEN  31
+#define L2CC_PROT_mskMRWEN  (0x1UL << L2CC_PROT_offMRWEN)
+
+/**
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ */
+#define L2CC_CTRL_offEN 31
+#define L2CC_CTRL_mskEN (0x1UL << L2CC_CTRL_offEN)
+
+/**
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ */
+#define L2_CCTL_STATUS_offCMD_COMP  31
+#define L2_CCTL_STATUS_mskCMD_COMP  (0x1 << L2_CCTL_STATUS_offCMD_COMP)
+

[PATCH 20/31] nds32: L2 cache support

[Greentime Hu]

From: Greentime Hu 

Signed-off-by: Vincent Chen 
Signed-off-by: Greentime Hu 
---
 arch/nds32/include/asm/l2_cache.h |  158 +
 arch/nds32/kernel/atl2c.c |   77 ++
 2 files changed, 235 insertions(+)
 create mode 100644 arch/nds32/include/asm/l2_cache.h
 create mode 100644 arch/nds32/kernel/atl2c.c

diff --git a/arch/nds32/include/asm/l2_cache.h 
b/arch/nds32/include/asm/l2_cache.h
new file mode 100644
index 000..b8530bd
--- /dev/null
+++ b/arch/nds32/include/asm/l2_cache.h
@@ -0,0 +1,158 @@
+/*
+ * Copyright (C) 2005-2017 Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#ifndef L2_CACHE_H
+#define L2_CACHE_H
+
+/* This is defined for head.S to use due to device tree is not yet built. */
+#define L2CC_PA_BASE   0x90F0
+
+/* CCTL_CMD_OP */
+#define L2_CA_CONF_OFF 0x0
+#defineL2_IF_CONF_OFF  0x4
+#define L2CC_SETUP_OFF 0x8
+#define L2CC_PROT_OFF  0xC
+#define L2CC_CTRL_OFF  0x10
+#define L2_INT_EN_OFF   0x20
+#define L2_STA_OFF  0x24
+#define RDERR_ADDR_OFF 0x28
+#define WRERR_ADDR_OFF 0x2c
+#define EVDPTERR_ADDR_OFF  0x30
+#define IMPL3ERR_ADDR_OFF  0x34
+#define L2_CNT0_CTRL_OFF0x40
+#define L2_EVNT_CNT0_OFF0x44
+#define L2_CNT1_CTRL_OFF0x48
+#define L2_EVNT_CNT1_OFF0x4c
+#define L2_CCTL_CMD_OFF0x60
+#define L2_CCTL_STATUS_OFF 0x64
+#define L2_LINE_TAG_OFF0x68
+#define L2_LINE_DPT_OFF0x70
+
+#define CCTL_CMD_L2_IX_INVAL0x0
+#define CCTL_CMD_L2_PA_INVAL0x1
+#define CCTL_CMD_L2_IX_WB   0x2
+#define CCTL_CMD_L2_PA_WB   0x3
+#define CCTL_CMD_L2_PA_WBINVAL  0x5
+#define CCTL_CMD_L2_SYNC0xa
+
+/* CCTL_CMD_TYPE */
+#define CCTL_SINGLE_CMD 0
+#define CCTL_BLOCK_CMD  0x10
+#define CCTL_ALL_CMD   0x10
+
+/**
+ * L2_CA_CONF (Cache architecture configuration)
+ */
+#define L2_CA_CONF_offL2SET0
+#define L2_CA_CONF_offL2WAY4
+#define L2_CA_CONF_offL2CLSZ8
+#define L2_CA_CONF_offL2DW 11
+#define L2_CA_CONF_offL2PT 14
+#define L2_CA_CONF_offL2VER16
+
+#define L2_CA_CONF_mskL2SET(0xFUL << L2_CA_CONF_offL2SET)
+#define L2_CA_CONF_mskL2WAY(0xFUL << L2_CA_CONF_offL2WAY)
+#define L2_CA_CONF_mskL2CLSZ(0x7UL << L2_CA_CONF_offL2CLSZ)
+#define L2_CA_CONF_mskL2DW (0x7UL << L2_CA_CONF_offL2DW)
+#define L2_CA_CONF_mskL2PT (0x3UL << L2_CA_CONF_offL2PT)
+#define L2_CA_CONF_mskL2VER(0xUL << L2_CA_CONF_offL2VER)
+
+/**
+ * L2CC_SETUP (L2CC Setup register)
+ */
+#define L2CC_SETUP_offPART  0
+#define L2CC_SETUP_mskPART  (0x3UL << L2CC_SETUP_offPART)
+#define L2CC_SETUP_offDDLATC4
+#define L2CC_SETUP_mskDDLATC(0x3UL << L2CC_SETUP_offDDLATC)
+#define L2CC_SETUP_offTDLATC8
+#define L2CC_SETUP_mskTDLATC(0x3UL << L2CC_SETUP_offTDLATC)
+
+/**
+ * L2CC_PROT (L2CC Protect register)
+ */
+#define L2CC_PROT_offMRWEN  31
+#define L2CC_PROT_mskMRWEN  (0x1UL << L2CC_PROT_offMRWEN)
+
+/**
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ */
+#define L2CC_CTRL_offEN 31
+#define L2CC_CTRL_mskEN (0x1UL << L2CC_CTRL_offEN)
+
+/**
+ * L2_CCTL_STATUS_Mn (The L2CCTL command working status for Master n)
+ */
+#define L2_CCTL_STATUS_offCMD_COMP  31
+#define L2_CCTL_STATUS_mskCMD_COMP  (0x1 << L2_CCTL_STATUS_offCMD_COMP)
+
+#ifndef __ASSEMBLY__
+extern void __iomem *atl2c_base;
+
+#include 
+#include