Re: [PATCH 21/22] ARM: sunxi: Add Allwinner A23 dtsi

2014-05-25 Thread Chen-Yu Tsai 
On Mon, May 26, 2014 at 3:38 AM, Maxime Ripard
 wrote:
> On Fri, May 23, 2014 at 03:51:24PM +0800, Chen-Yu Tsai wrote:
>> The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores
>> and a Mali-400MP2 GPU.
>>
>> Signed-off-by: Chen-Yu Tsai 
>> ---
>>  arch/arm/boot/dts/sun8i-a23.dtsi | 524 
>> +++
>>  1 file changed, 524 insertions(+)
>>  create mode 100644 arch/arm/boot/dts/sun8i-a23.dtsi
>>
>> diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi 
>> b/arch/arm/boot/dts/sun8i-a23.dtsi
>> new file mode 100644
>> index 000..1cff087
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-a23.dtsi
>> @@ -0,0 +1,524 @@
>> +/*
>> + * Copyright 2014 Chen-Yu Tsai
>> + *
>> + * Chen-Yu Tsai 
>> + *
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +
>> +/include/ "skeleton.dtsi"
>> +
>> +/ {
>> + interrupt-parent = <>;
>> +
>> + aliases {
>> + serial0 = 
>> + serial1 = 
>> + serial2 = 
>> + serial3 = 
>> + serial4 = 
>> + serial5 = _uart;
>> + };
>> +
>> +
>> + cpus {
>> + enable-method = "allwinner,sun8i-a23";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu@0 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <0>;
>> + clocks = <>;
>> + };
>> +
>> + cpu@1 {
>> + compatible = "arm,cortex-a7";
>> + device_type = "cpu";
>> + reg = <1>;
>> + clocks = <>;
>
> The clocks attributes have not been merged yet.

I'll drop them until they are merged.

>> + };
>> + };
>> +
>> + memory {
>> + reg = <0x4000 0x8000>;
>> + };
>> +
>> + pmu {
>> + compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
>> + interrupts = <0 120 4>,
>> +  <0 121 4>,
>> +  <0 122 4>,
>> +  <0 123 4>;
>> + };
>
> The PMU usually have as much interrupts as CPU core, so this is most
> likely wrong.

I see. I just copied the interrupts that were listed in Allwinner sources.
I'll drop the extra 2.

> Also, do you know if the arch timers are usable on the A23?

I tried them (copying the "timer" section from A20 dtsi), but the system
just hangs. I think I'll leave this for a follow up series.

>> +
>> + clocks {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + osc24M: osc24M_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <2400>;
>> + clock-output-names = "osc24M";
>> + };
>> +
>> + osc32k: osc32k_clk {
>> + #clock-cells = <0>;
>> + compatible = "fixed-clock";
>> + clock-frequency = <32768>;
>> + clock-output-names = "osc32k";
>> + };
>> +
>> + pll1: clk@01c2 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun8i-a23-pll1-clk";
>> + reg = <0x01c2 0x4>;
>> + clocks = <>;
>> + clock-output-names = "pll1";
>> + };
>> +
>> + pll6: clk@01c20028 {
>> + #clock-cells = <1>;
>> + compatible = "allwinner,sun6i-a31-pll6-clk";
>> + reg = <0x01c20028 0x4>;
>> + clocks = <>;
>> + clock-output-names = "pll6_other", "pll6";
>> + };
>> +
>> + cpu: cpu_clk@01c20050 {
>> + #clock-cells = <0>;
>> + compatible = "allwinner,sun4i-a10-cpu-clk";
>> + reg = <0x01c20050 0x4>;
>> +
>> + /*
>> +  * PLL1 is listed twice here.
>> +  * While it looks suspicious, it's actually documented
>> +  * that way both in the datasheet and in the code from
>> +  * Allwinner.
>> +  */
>> + clocks = <>, <>, <>, <>;
>> + clock-output-names = "cpu";
>> + };
>> +
>> + axi: axi_clk@01c20050 {
>> + #clock-cells = <0>;
>> + /*
>> +  * AXI clock on A23 is actually wider,
>> +  * but extra bit is useless for

Re: [PATCH 21/22] ARM: sunxi: Add Allwinner A23 dtsi

2014-05-25 Thread Maxime Ripard 
On Fri, May 23, 2014 at 03:51:24PM +0800, Chen-Yu Tsai wrote:
> The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores
> and a Mali-400MP2 GPU.
> 
> Signed-off-by: Chen-Yu Tsai 
> ---
>  arch/arm/boot/dts/sun8i-a23.dtsi | 524 
> +++
>  1 file changed, 524 insertions(+)
>  create mode 100644 arch/arm/boot/dts/sun8i-a23.dtsi
> 
> diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi 
> b/arch/arm/boot/dts/sun8i-a23.dtsi
> new file mode 100644
> index 000..1cff087
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-a23.dtsi
> @@ -0,0 +1,524 @@
> +/*
> + * Copyright 2014 Chen-Yu Tsai
> + *
> + * Chen-Yu Tsai 
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/include/ "skeleton.dtsi"
> +
> +/ {
> + interrupt-parent = <>;
> +
> + aliases {
> + serial0 = 
> + serial1 = 
> + serial2 = 
> + serial3 = 
> + serial4 = 
> + serial5 = _uart;
> + };
> +
> +
> + cpus {
> + enable-method = "allwinner,sun8i-a23";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0>;
> + clocks = <>;
> + };
> +
> + cpu@1 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <1>;
> + clocks = <>;

The clocks attributes have not been merged yet.

> + };
> + };
> +
> + memory {
> + reg = <0x4000 0x8000>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
> + interrupts = <0 120 4>,
> +  <0 121 4>,
> +  <0 122 4>,
> +  <0 123 4>;
> + };

The PMU usually have as much interrupts as CPU core, so this is most
likely wrong.

Also, do you know if the arch timers are usable on the A23?

> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + osc24M: osc24M_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <2400>;
> + clock-output-names = "osc24M";
> + };
> +
> + osc32k: osc32k_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "osc32k";
> + };
> +
> + pll1: clk@01c2 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun8i-a23-pll1-clk";
> + reg = <0x01c2 0x4>;
> + clocks = <>;
> + clock-output-names = "pll1";
> + };
> +
> + pll6: clk@01c20028 {
> + #clock-cells = <1>;
> + compatible = "allwinner,sun6i-a31-pll6-clk";
> + reg = <0x01c20028 0x4>;
> + clocks = <>;
> + clock-output-names = "pll6_other", "pll6";
> + };
> +
> + cpu: cpu_clk@01c20050 {
> + #clock-cells = <0>;
> + compatible = "allwinner,sun4i-a10-cpu-clk";
> + reg = <0x01c20050 0x4>;
> +
> + /*
> +  * PLL1 is listed twice here.
> +  * While it looks suspicious, it's actually documented
> +  * that way both in the datasheet and in the code from
> +  * Allwinner.
> +  */
> + clocks = <>, <>, <>, <>;
> + clock-output-names = "cpu";
> + };
> +
> + axi: axi_clk@01c20050 {
> + #clock-cells = <0>;
> + /*
> +  * AXI clock on A23 is actually wider,
> +  * but extra bit is useless for divider
> +  */

Then please add a new compatible for this, even though we're not doing
anything differently (yet).

> + compatible = "allwinner,sun4i-a10-axi-clk";
> + reg = <0x01c20050 0x4>;
> + clocks = <>;
> + clock-output-names = "axi";
> + };
> +
> + ahb1_pll6: ahb1_pll6_clk@01c20054 {
> + #clock-cells = <0>;
> +

Re: [PATCH 21/22] ARM: sunxi: Add Allwinner A23 dtsi

2014-05-25 Thread Maxime Ripard 
On Fri, May 23, 2014 at 03:51:24PM +0800, Chen-Yu Tsai wrote:
 The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores
 and a Mali-400MP2 GPU.
 
 Signed-off-by: Chen-Yu Tsai w...@csie.org
 ---
  arch/arm/boot/dts/sun8i-a23.dtsi | 524 
 +++
  1 file changed, 524 insertions(+)
  create mode 100644 arch/arm/boot/dts/sun8i-a23.dtsi
 
 diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi 
 b/arch/arm/boot/dts/sun8i-a23.dtsi
 new file mode 100644
 index 000..1cff087
 --- /dev/null
 +++ b/arch/arm/boot/dts/sun8i-a23.dtsi
 @@ -0,0 +1,524 @@
 +/*
 + * Copyright 2014 Chen-Yu Tsai
 + *
 + * Chen-Yu Tsai w...@csie.org
 + *
 + * The code contained herein is licensed under the GNU General Public
 + * License. You may obtain a copy of the GNU General Public License
 + * Version 2 or later at the following locations:
 + *
 + * http://www.opensource.org/licenses/gpl-license.html
 + * http://www.gnu.org/copyleft/gpl.html
 + */
 +
 +/include/ skeleton.dtsi
 +
 +/ {
 + interrupt-parent = gic;
 +
 + aliases {
 + serial0 = uart0;
 + serial1 = uart1;
 + serial2 = uart2;
 + serial3 = uart3;
 + serial4 = uart4;
 + serial5 = r_uart;
 + };
 +
 +
 + cpus {
 + enable-method = allwinner,sun8i-a23;
 + #address-cells = 1;
 + #size-cells = 0;
 +
 + cpu@0 {
 + compatible = arm,cortex-a7;
 + device_type = cpu;
 + reg = 0;
 + clocks = cpu;
 + };
 +
 + cpu@1 {
 + compatible = arm,cortex-a7;
 + device_type = cpu;
 + reg = 1;
 + clocks = cpu;

The clocks attributes have not been merged yet.

 + };
 + };
 +
 + memory {
 + reg = 0x4000 0x8000;
 + };
 +
 + pmu {
 + compatible = arm,cortex-a7-pmu, arm,cortex-a15-pmu;
 + interrupts = 0 120 4,
 +  0 121 4,
 +  0 122 4,
 +  0 123 4;
 + };

The PMU usually have as much interrupts as CPU core, so this is most
likely wrong.

Also, do you know if the arch timers are usable on the A23?

 +
 + clocks {
 + #address-cells = 1;
 + #size-cells = 1;
 + ranges;
 +
 + osc24M: osc24M_clk {
 + #clock-cells = 0;
 + compatible = fixed-clock;
 + clock-frequency = 2400;
 + clock-output-names = osc24M;
 + };
 +
 + osc32k: osc32k_clk {
 + #clock-cells = 0;
 + compatible = fixed-clock;
 + clock-frequency = 32768;
 + clock-output-names = osc32k;
 + };
 +
 + pll1: clk@01c2 {
 + #clock-cells = 0;
 + compatible = allwinner,sun8i-a23-pll1-clk;
 + reg = 0x01c2 0x4;
 + clocks = osc24M;
 + clock-output-names = pll1;
 + };
 +
 + pll6: clk@01c20028 {
 + #clock-cells = 1;
 + compatible = allwinner,sun6i-a31-pll6-clk;
 + reg = 0x01c20028 0x4;
 + clocks = osc24M;
 + clock-output-names = pll6_other, pll6;
 + };
 +
 + cpu: cpu_clk@01c20050 {
 + #clock-cells = 0;
 + compatible = allwinner,sun4i-a10-cpu-clk;
 + reg = 0x01c20050 0x4;
 +
 + /*
 +  * PLL1 is listed twice here.
 +  * While it looks suspicious, it's actually documented
 +  * that way both in the datasheet and in the code from
 +  * Allwinner.
 +  */
 + clocks = osc32k, osc24M, pll1, pll1;
 + clock-output-names = cpu;
 + };
 +
 + axi: axi_clk@01c20050 {
 + #clock-cells = 0;
 + /*
 +  * AXI clock on A23 is actually wider,
 +  * but extra bit is useless for divider
 +  */

Then please add a new compatible for this, even though we're not doing
anything differently (yet).

 + compatible = allwinner,sun4i-a10-axi-clk;
 + reg = 0x01c20050 0x4;
 + clocks = cpu;
 + clock-output-names = axi;
 + };
 +
 + ahb1_pll6: ahb1_pll6_clk@01c20054 {
 + #clock-cells = 0;
 + compatible = allwinner,sun6i-a31-ahb1-pll6-clk;
 + reg = 0x01c20054 0x4;
 + clocks = pll6 0;
 +

Re: [PATCH 21/22] ARM: sunxi: Add Allwinner A23 dtsi

2014-05-25 Thread Chen-Yu Tsai 
On Mon, May 26, 2014 at 3:38 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
 On Fri, May 23, 2014 at 03:51:24PM +0800, Chen-Yu Tsai wrote:
 The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores
 and a Mali-400MP2 GPU.

 Signed-off-by: Chen-Yu Tsai w...@csie.org
 ---
  arch/arm/boot/dts/sun8i-a23.dtsi | 524 
 +++
  1 file changed, 524 insertions(+)
  create mode 100644 arch/arm/boot/dts/sun8i-a23.dtsi

 diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi 
 b/arch/arm/boot/dts/sun8i-a23.dtsi
 new file mode 100644
 index 000..1cff087
 --- /dev/null
 +++ b/arch/arm/boot/dts/sun8i-a23.dtsi
 @@ -0,0 +1,524 @@
 +/*
 + * Copyright 2014 Chen-Yu Tsai
 + *
 + * Chen-Yu Tsai w...@csie.org
 + *
 + * The code contained herein is licensed under the GNU General Public
 + * License. You may obtain a copy of the GNU General Public License
 + * Version 2 or later at the following locations:
 + *
 + * http://www.opensource.org/licenses/gpl-license.html
 + * http://www.gnu.org/copyleft/gpl.html
 + */
 +
 +/include/ skeleton.dtsi
 +
 +/ {
 + interrupt-parent = gic;
 +
 + aliases {
 + serial0 = uart0;
 + serial1 = uart1;
 + serial2 = uart2;
 + serial3 = uart3;
 + serial4 = uart4;
 + serial5 = r_uart;
 + };
 +
 +
 + cpus {
 + enable-method = allwinner,sun8i-a23;
 + #address-cells = 1;
 + #size-cells = 0;
 +
 + cpu@0 {
 + compatible = arm,cortex-a7;
 + device_type = cpu;
 + reg = 0;
 + clocks = cpu;
 + };
 +
 + cpu@1 {
 + compatible = arm,cortex-a7;
 + device_type = cpu;
 + reg = 1;
 + clocks = cpu;

 The clocks attributes have not been merged yet.

I'll drop them until they are merged.

 + };
 + };
 +
 + memory {
 + reg = 0x4000 0x8000;
 + };
 +
 + pmu {
 + compatible = arm,cortex-a7-pmu, arm,cortex-a15-pmu;
 + interrupts = 0 120 4,
 +  0 121 4,
 +  0 122 4,
 +  0 123 4;
 + };

 The PMU usually have as much interrupts as CPU core, so this is most
 likely wrong.

I see. I just copied the interrupts that were listed in Allwinner sources.
I'll drop the extra 2.

 Also, do you know if the arch timers are usable on the A23?

I tried them (copying the timer section from A20 dtsi), but the system
just hangs. I think I'll leave this for a follow up series.

 +
 + clocks {
 + #address-cells = 1;
 + #size-cells = 1;
 + ranges;
 +
 + osc24M: osc24M_clk {
 + #clock-cells = 0;
 + compatible = fixed-clock;
 + clock-frequency = 2400;
 + clock-output-names = osc24M;
 + };
 +
 + osc32k: osc32k_clk {
 + #clock-cells = 0;
 + compatible = fixed-clock;
 + clock-frequency = 32768;
 + clock-output-names = osc32k;
 + };
 +
 + pll1: clk@01c2 {
 + #clock-cells = 0;
 + compatible = allwinner,sun8i-a23-pll1-clk;
 + reg = 0x01c2 0x4;
 + clocks = osc24M;
 + clock-output-names = pll1;
 + };
 +
 + pll6: clk@01c20028 {
 + #clock-cells = 1;
 + compatible = allwinner,sun6i-a31-pll6-clk;
 + reg = 0x01c20028 0x4;
 + clocks = osc24M;
 + clock-output-names = pll6_other, pll6;
 + };
 +
 + cpu: cpu_clk@01c20050 {
 + #clock-cells = 0;
 + compatible = allwinner,sun4i-a10-cpu-clk;
 + reg = 0x01c20050 0x4;
 +
 + /*
 +  * PLL1 is listed twice here.
 +  * While it looks suspicious, it's actually documented
 +  * that way both in the datasheet and in the code from
 +  * Allwinner.
 +  */
 + clocks = osc32k, osc24M, pll1, pll1;
 + clock-output-names = cpu;
 + };
 +
 + axi: axi_clk@01c20050 {
 + #clock-cells = 0;
 + /*
 +  * AXI clock on A23 is actually wider,
 +  * but extra bit is useless for divider
 +  */

 Then please add a new compatible for this, even though we're not doing
 anything differently (yet).

Will do.

 + compatible = allwinner,sun4i-a10-axi-clk;
 + reg =

[PATCH 21/22] ARM: sunxi: Add Allwinner A23 dtsi

2014-05-23 Thread Chen-Yu Tsai 
The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores
and a Mali-400MP2 GPU.

Signed-off-by: Chen-Yu Tsai 
---
 arch/arm/boot/dts/sun8i-a23.dtsi | 524 +++
 1 file changed, 524 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-a23.dtsi

diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
new file mode 100644
index 000..1cff087
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -0,0 +1,524 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai 
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+   interrupt-parent = <>;
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   serial3 = 
+   serial4 = 
+   serial5 = _uart;
+   };
+
+
+   cpus {
+   enable-method = "allwinner,sun8i-a23";
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <0>;
+   clocks = <>;
+   };
+
+   cpu@1 {
+   compatible = "arm,cortex-a7";
+   device_type = "cpu";
+   reg = <1>;
+   clocks = <>;
+   };
+   };
+
+   memory {
+   reg = <0x4000 0x8000>;
+   };
+
+   pmu {
+   compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+   interrupts = <0 120 4>,
+<0 121 4>,
+<0 122 4>,
+<0 123 4>;
+   };
+
+   clocks {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges;
+
+   osc24M: osc24M_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <2400>;
+   clock-output-names = "osc24M";
+   };
+
+   osc32k: osc32k_clk {
+   #clock-cells = <0>;
+   compatible = "fixed-clock";
+   clock-frequency = <32768>;
+   clock-output-names = "osc32k";
+   };
+
+   pll1: clk@01c2 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun8i-a23-pll1-clk";
+   reg = <0x01c2 0x4>;
+   clocks = <>;
+   clock-output-names = "pll1";
+   };
+
+   pll6: clk@01c20028 {
+   #clock-cells = <1>;
+   compatible = "allwinner,sun6i-a31-pll6-clk";
+   reg = <0x01c20028 0x4>;
+   clocks = <>;
+   clock-output-names = "pll6_other", "pll6";
+   };
+
+   cpu: cpu_clk@01c20050 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun4i-a10-cpu-clk";
+   reg = <0x01c20050 0x4>;
+
+   /*
+* PLL1 is listed twice here.
+* While it looks suspicious, it's actually documented
+* that way both in the datasheet and in the code from
+* Allwinner.
+*/
+   clocks = <>, <>, <>, <>;
+   clock-output-names = "cpu";
+   };
+
+   axi: axi_clk@01c20050 {
+   #clock-cells = <0>;
+   /*
+* AXI clock on A23 is actually wider,
+* but extra bit is useless for divider
+*/
+   compatible = "allwinner,sun4i-a10-axi-clk";
+   reg = <0x01c20050 0x4>;
+   clocks = <>;
+   clock-output-names = "axi";
+   };
+
+   ahb1_pll6: ahb1_pll6_clk@01c20054 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun6i-a31-ahb1-pll6-clk";
+   reg = <0x01c20054 0x4>;
+   clocks = < 0>;
+   clock-output-names = "ahb1_pll6";
+   };
+
+   ahb1_mux: ahb1_mux_clk@01c20054 {
+   #clock-cells = <0>;
+   compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
+   reg = <0x01c20054 0x4>;
+

[PATCH 21/22] ARM: sunxi: Add Allwinner A23 dtsi

2014-05-23 Thread Chen-Yu Tsai 
The Allwinner A23 is a tablet oriented SoC with 2 Cortex-A7 cores
and a Mali-400MP2 GPU.

Signed-off-by: Chen-Yu Tsai w...@csie.org
---
 arch/arm/boot/dts/sun8i-a23.dtsi | 524 +++
 1 file changed, 524 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-a23.dtsi

diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
new file mode 100644
index 000..1cff087
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -0,0 +1,524 @@
+/*
+ * Copyright 2014 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai w...@csie.org
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ skeleton.dtsi
+
+/ {
+   interrupt-parent = gic;
+
+   aliases {
+   serial0 = uart0;
+   serial1 = uart1;
+   serial2 = uart2;
+   serial3 = uart3;
+   serial4 = uart4;
+   serial5 = r_uart;
+   };
+
+
+   cpus {
+   enable-method = allwinner,sun8i-a23;
+   #address-cells = 1;
+   #size-cells = 0;
+
+   cpu@0 {
+   compatible = arm,cortex-a7;
+   device_type = cpu;
+   reg = 0;
+   clocks = cpu;
+   };
+
+   cpu@1 {
+   compatible = arm,cortex-a7;
+   device_type = cpu;
+   reg = 1;
+   clocks = cpu;
+   };
+   };
+
+   memory {
+   reg = 0x4000 0x8000;
+   };
+
+   pmu {
+   compatible = arm,cortex-a7-pmu, arm,cortex-a15-pmu;
+   interrupts = 0 120 4,
+0 121 4,
+0 122 4,
+0 123 4;
+   };
+
+   clocks {
+   #address-cells = 1;
+   #size-cells = 1;
+   ranges;
+
+   osc24M: osc24M_clk {
+   #clock-cells = 0;
+   compatible = fixed-clock;
+   clock-frequency = 2400;
+   clock-output-names = osc24M;
+   };
+
+   osc32k: osc32k_clk {
+   #clock-cells = 0;
+   compatible = fixed-clock;
+   clock-frequency = 32768;
+   clock-output-names = osc32k;
+   };
+
+   pll1: clk@01c2 {
+   #clock-cells = 0;
+   compatible = allwinner,sun8i-a23-pll1-clk;
+   reg = 0x01c2 0x4;
+   clocks = osc24M;
+   clock-output-names = pll1;
+   };
+
+   pll6: clk@01c20028 {
+   #clock-cells = 1;
+   compatible = allwinner,sun6i-a31-pll6-clk;
+   reg = 0x01c20028 0x4;
+   clocks = osc24M;
+   clock-output-names = pll6_other, pll6;
+   };
+
+   cpu: cpu_clk@01c20050 {
+   #clock-cells = 0;
+   compatible = allwinner,sun4i-a10-cpu-clk;
+   reg = 0x01c20050 0x4;
+
+   /*
+* PLL1 is listed twice here.
+* While it looks suspicious, it's actually documented
+* that way both in the datasheet and in the code from
+* Allwinner.
+*/
+   clocks = osc32k, osc24M, pll1, pll1;
+   clock-output-names = cpu;
+   };
+
+   axi: axi_clk@01c20050 {
+   #clock-cells = 0;
+   /*
+* AXI clock on A23 is actually wider,
+* but extra bit is useless for divider
+*/
+   compatible = allwinner,sun4i-a10-axi-clk;
+   reg = 0x01c20050 0x4;
+   clocks = cpu;
+   clock-output-names = axi;
+   };
+
+   ahb1_pll6: ahb1_pll6_clk@01c20054 {
+   #clock-cells = 0;
+   compatible = allwinner,sun6i-a31-ahb1-pll6-clk;
+   reg = 0x01c20054 0x4;
+   clocks = pll6 0;
+   clock-output-names = ahb1_pll6;
+   };
+
+   ahb1_mux: ahb1_mux_clk@01c20054 {
+   #clock-cells = 0;
+   compatible = allwinner,sun6i-a31-ahb1-mux-clk;
+   reg = 0x01c20054 0x4;
+   clocks =