Re: [PATCH 22/22] arm64: dts: qcom: sm8150: Add APSS shared mailbox

[Vinod Koul]

On 20-08-19, 11:50, Sibi Sankar wrote:
> Hey Vinod,
> 
> There seems to be a mismatch
> between the commit description
> and the dt node (This is the
> aoss qmp node not the APPS
> shared node).

Thanks for pointing, I have squashed this and other into single patch
and updated the description

> 
> 
> On 2019-08-19 23:11, Vinod Koul wrote:
> > On 14-08-19, 10:17, Stephen Boyd wrote:
> > > Quoting Vinod Koul (2019-08-14 05:50:12)
> > > > @@ -338,6 +339,16 @@
> > > > #interrupt-cells = <2>;
> > > > };
> > > >
> > > > +   aoss_qmp: qmp@c30 {
> > > 
> > > Node name of 'clock-controller', or 'power-controller'?
> > 
> > The orignal entry for sdm845 has no such statement, but yes it doesn
> > makes sense. I am thinking power-controller.. Bjorn?
> 
> aoss_qmp registers both pd and
> clock providers.

Thats correct, I chatted with Bjorn and he recommended we use power-controller

-- 
~Vinod

Re: [PATCH 22/22] arm64: dts: qcom: sm8150: Add APSS shared mailbox

[Sibi Sankar]

Hey Vinod,

There seems to be a mismatch
between the commit description
and the dt node (This is the
aoss qmp node not the APPS
shared node).


On 2019-08-19 23:11, Vinod Koul wrote:

On 14-08-19, 10:17, Stephen Boyd wrote:

Quoting Vinod Koul (2019-08-14 05:50:12)
> @@ -338,6 +339,16 @@
> #interrupt-cells = <2>;
> };
>
> +   aoss_qmp: qmp@c30 {

Node name of 'clock-controller', or 'power-controller'?


The orignal entry for sdm845 has no such statement, but yes it doesn
makes sense. I am thinking power-controller.. Bjorn?


aoss_qmp registers both pd and
clock providers.

--
-- Sibi Sankar --
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.

Re: [PATCH 22/22] arm64: dts: qcom: sm8150: Add APSS shared mailbox

[Vinod Koul]

On 14-08-19, 10:17, Stephen Boyd wrote:
> Quoting Vinod Koul (2019-08-14 05:50:12)
> > @@ -338,6 +339,16 @@
> > #interrupt-cells = <2>;
> > };
> >  
> > +   aoss_qmp: qmp@c30 {
> 
> Node name of 'clock-controller', or 'power-controller'?

The orignal entry for sdm845 has no such statement, but yes it doesn
makes sense. I am thinking power-controller.. Bjorn?

-- 
~Vinod

Re: [PATCH 22/22] arm64: dts: qcom: sm8150: Add APSS shared mailbox

[Stephen Boyd]

Quoting Vinod Koul (2019-08-14 05:50:12)
> @@ -338,6 +339,16 @@
> #interrupt-cells = <2>;
> };
>  
> +   aoss_qmp: qmp@c30 {

Node name of 'clock-controller', or 'power-controller'?

> +   compatible = "qcom,sm8150-aoss-qmp";
> +   reg = <0x0c30 0x10>;
> +   interrupts = ;
> +   mboxes = <_shared 0>;

[PATCH 22/22] arm64: dts: qcom: sm8150: Add APSS shared mailbox

[Vinod Koul]

From: Sibi Sankar 

Add APSS shared mailbox support to SM8150 SoC.

Signed-off-by: Sibi Sankar 
Signed-off-by: Vinod Koul 
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi 
b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index 5df3f335272a..88cbab4a9297 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -5,6 +5,7 @@
 #include 
 #include 
 #include 
+#include 
 
 / {
interrupt-parent = <>;
@@ -338,6 +339,16 @@
#interrupt-cells = <2>;
};
 
+   aoss_qmp: qmp@c30 {
+   compatible = "qcom,sm8150-aoss-qmp";
+   reg = <0x0c30 0x10>;
+   interrupts = ;
+   mboxes = <_shared 0>;
+
+   #clock-cells = <0>;
+   #power-domain-cells = <1>;
+   };
+
intc: interrupt-controller@17a0 {
compatible = "arm,gic-v3";
interrupt-controller;
-- 
2.20.1