subject:"\[PATCH 3\/7\] drm\/msm\/a5xx\: Add support for Adreno 508, 509, 512 GPUs"

Re: [PATCH 3/7] drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs

2020-09-28 Thread Jordan Crouse

On Sat, Sep 26, 2020 at 02:51:42PM +0200, khol...@gmail.com wrote:
> From: AngeloGioacchino Del Regno 
> 
> The Adreno 508/509/512 GPUs are stripped versions of the Adreno
> 5xx found in the mid-end SoCs such as SDM630, SDM636, SDM660 and
> SDA variants; these SoCs are usually provided with ZAP firmwares,
> but they have no available GPMU.

Reviewed-by: Jordan Crouse 

> Signed-off-by: AngeloGioacchino Del Regno 
> ---
>  drivers/gpu/drm/msm/adreno/a5xx_gpu.c  | 172 ++---
>  drivers/gpu/drm/msm/adreno/a5xx_power.c|   4 +-
>  drivers/gpu/drm/msm/adreno/adreno_device.c |  60 +++
>  drivers/gpu/drm/msm/adreno/adreno_gpu.h|  15 ++
>  4 files changed, 231 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
> b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> index f98f0844838c..9bcbf6cd5a28 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> @@ -212,7 +212,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct 
> msm_gem_submit *submit,
>   a5xx_preempt_trigger(gpu);
>  }
>  
> -static const struct {
> +static const struct adreno_five_hwcg_regs {
>   u32 offset;
>   u32 value;
>  } a5xx_hwcg[] = {
> @@ -308,16 +308,124 @@ static const struct {
>   {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x4000},
>   {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x0200},
>   {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x}
> +}, a50x_hwcg[] = {
> + {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x0222},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x0220},
> + {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0xF3CF},
> + {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x0080},
> + {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x0022},
> + {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00F4},
> + {REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x0002},
> + {REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x0022},
> + {REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x0000},
> + {REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x0552},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x0050},
> + {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
> + {REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
> + {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x0002},
> + {REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
> + {REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x0422},
> + {REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x0222},
> + {REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
> + {REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x4000},
> + {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x0200},
> + {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x},
> +}, a512_hwcg[] = {
> + {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x0222},
> + {REG_A5XX_RBBM_CLOCK_CNTL_SP1, 0x0222},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x0220},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_SP1, 0x0220},
> + {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0xF3CF},
> + {REG_A5XX_RBBM_CLOCK_HYST_SP1, 0xF3CF},
> + {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x0080},
> + {REG_A5XX_RBBM_CLOCK_DELAY_SP1, 0x0080},
> + {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL2_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL3_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST2_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_HYST3_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY2_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x},
> + {REG_A5XX_RBBM_CLOCK_DELAY3_TP1, 0x},
> + {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x},
> +

Re: [PATCH 3/7] drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs

2020-09-26 Thread Martin Botka

Tested on Xperia 10
Tested-by: Martin Botka

[PATCH 3/7] drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs

2020-09-26 Thread kholk11

From: AngeloGioacchino Del Regno 

The Adreno 508/509/512 GPUs are stripped versions of the Adreno
5xx found in the mid-end SoCs such as SDM630, SDM636, SDM660 and
SDA variants; these SoCs are usually provided with ZAP firmwares,
but they have no available GPMU.

Signed-off-by: AngeloGioacchino Del Regno 
---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c  | 172 ++---
 drivers/gpu/drm/msm/adreno/a5xx_power.c|   4 +-
 drivers/gpu/drm/msm/adreno/adreno_device.c |  60 +++
 drivers/gpu/drm/msm/adreno/adreno_gpu.h|  15 ++
 4 files changed, 231 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c 
b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index f98f0844838c..9bcbf6cd5a28 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -212,7 +212,7 @@ static void a5xx_submit(struct msm_gpu *gpu, struct 
msm_gem_submit *submit,
a5xx_preempt_trigger(gpu);
 }
 
-static const struct {
+static const struct adreno_five_hwcg_regs {
u32 offset;
u32 value;
 } a5xx_hwcg[] = {
@@ -308,16 +308,124 @@ static const struct {
{REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x4000},
{REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x0200},
{REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x}
+}, a50x_hwcg[] = {
+   {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x0222},
+   {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x0220},
+   {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0xF3CF},
+   {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x0080},
+   {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x},
+   {REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x},
+   {REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x0022},
+   {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x},
+   {REG_A5XX_RBBM_CLOCK_HYST_UCHE, 0x00F4},
+   {REG_A5XX_RBBM_CLOCK_DELAY_UCHE, 0x0002},
+   {REG_A5XX_RBBM_CLOCK_CNTL_RB0, 0x},
+   {REG_A5XX_RBBM_CLOCK_CNTL2_RB0, 0x0022},
+   {REG_A5XX_RBBM_CLOCK_CNTL_CCU0, 0x0000},
+   {REG_A5XX_RBBM_CLOCK_CNTL_RAC, 0x0552},
+   {REG_A5XX_RBBM_CLOCK_CNTL2_RAC, 0x0050},
+   {REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0, 0x04040404},
+   {REG_A5XX_RBBM_CLOCK_HYST_RAC, 0x07444044},
+   {REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0, 0x0002},
+   {REG_A5XX_RBBM_CLOCK_DELAY_RAC, 0x00010011},
+   {REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x0422},
+   {REG_A5XX_RBBM_CLOCK_MODE_GPC, 0x0222},
+   {REG_A5XX_RBBM_CLOCK_MODE_VFD, 0x},
+   {REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x},
+   {REG_A5XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+   {REG_A5XX_RBBM_CLOCK_HYST_VFD, 0x},
+   {REG_A5XX_RBBM_CLOCK_DELAY_HLSQ, 0x},
+   {REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x4000},
+   {REG_A5XX_RBBM_CLOCK_DELAY_GPC, 0x0200},
+   {REG_A5XX_RBBM_CLOCK_DELAY_VFD, 0x},
+}, a512_hwcg[] = {
+   {REG_A5XX_RBBM_CLOCK_CNTL_SP0, 0x0222},
+   {REG_A5XX_RBBM_CLOCK_CNTL_SP1, 0x0222},
+   {REG_A5XX_RBBM_CLOCK_CNTL2_SP0, 0x0220},
+   {REG_A5XX_RBBM_CLOCK_CNTL2_SP1, 0x0220},
+   {REG_A5XX_RBBM_CLOCK_HYST_SP0, 0xF3CF},
+   {REG_A5XX_RBBM_CLOCK_HYST_SP1, 0xF3CF},
+   {REG_A5XX_RBBM_CLOCK_DELAY_SP0, 0x0080},
+   {REG_A5XX_RBBM_CLOCK_DELAY_SP1, 0x0080},
+   {REG_A5XX_RBBM_CLOCK_CNTL_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_CNTL_TP1, 0x},
+   {REG_A5XX_RBBM_CLOCK_CNTL2_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_CNTL2_TP1, 0x},
+   {REG_A5XX_RBBM_CLOCK_CNTL3_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_CNTL3_TP1, 0x},
+   {REG_A5XX_RBBM_CLOCK_HYST_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_HYST_TP1, 0x},
+   {REG_A5XX_RBBM_CLOCK_HYST2_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_HYST2_TP1, 0x},
+   {REG_A5XX_RBBM_CLOCK_HYST3_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_HYST3_TP1, 0x},
+   {REG_A5XX_RBBM_CLOCK_DELAY_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_DELAY_TP1, 0x},
+   {REG_A5XX_RBBM_CLOCK_DELAY2_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_DELAY2_TP1, 0x},
+   {REG_A5XX_RBBM_CLOCK_DELAY3_TP0, 0x},
+   {REG_A5XX_RBBM_CLOCK_DELAY3_TP1, 0x},
+   {REG_A5XX_RBBM_CLOCK_CNTL_UCHE, 0x},
+   {REG_A5XX_RBBM_CLOCK_CNTL2_UCHE, 0x},
+   {REG_A5XX_RBBM_CLOCK_CNTL3_UCHE, 0x},
+   {REG_A5XX_RBBM_CLOCK_CNTL4_UCHE, 0x0022},
+

Re: [PATCH 3/7] drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs

Re: [PATCH 3/7] drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs

[PATCH 3/7] drm/msm/a5xx: Add support for Adreno 508, 509, 512 GPUs

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