[PATCH 4 of 4] x86: update reference for PAE tlb flushing
Remove bogus reference to "Pentium-II erratum A13" and point to the actual canonical source of information about what requirements x86 processors have for PAE pagetable updates. Signed-off-by: Jeremy Fitzhardinge <[EMAIL PROTECTED]> --- include/asm-x86/pgalloc_32.h |6 -- include/asm-x86/pgtable-3level.h |6 -- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/include/asm-x86/pgalloc_32.h b/include/asm-x86/pgalloc_32.h --- a/include/asm-x86/pgalloc_32.h +++ b/include/asm-x86/pgalloc_32.h @@ -80,8 +80,10 @@ set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT)); /* -* Pentium-II erratum A13: in PAE mode we explicitly have to flush -* the TLB via cr3 if the top-level pgd is changed... +* According to Intel App note "TLBs, Paging-Structure Caches, +* and Their Invalidation", April 2007, document 317080-001, +* section 8.1: in PAE mode we explicitly have to flush the +* TLB via cr3 if the top-level pgd is changed... */ if (mm == current->active_mm) write_cr3(read_cr3()); diff --git a/include/asm-x86/pgtable-3level.h b/include/asm-x86/pgtable-3level.h --- a/include/asm-x86/pgtable-3level.h +++ b/include/asm-x86/pgtable-3level.h @@ -98,8 +98,10 @@ set_pud(pudp, __pud(0)); /* -* Pentium-II erratum A13: in PAE mode we explicitly have to flush -* the TLB via cr3 if the top-level pgd is changed... +* According to Intel App note "TLBs, Paging-Structure Caches, +* and Their Invalidation", April 2007, document 317080-001, +* section 8.1: in PAE mode we explicitly have to flush the +* TLB via cr3 if the top-level pgd is changed... * * Make sure the pud entry we're updating is within the * current pgd to avoid unnecessary TLB flushes. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 4 of 4] x86: update reference for PAE tlb flushing
Remove bogus reference to Pentium-II erratum A13 and point to the actual canonical source of information about what requirements x86 processors have for PAE pagetable updates. Signed-off-by: Jeremy Fitzhardinge [EMAIL PROTECTED] --- include/asm-x86/pgalloc_32.h |6 -- include/asm-x86/pgtable-3level.h |6 -- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/include/asm-x86/pgalloc_32.h b/include/asm-x86/pgalloc_32.h --- a/include/asm-x86/pgalloc_32.h +++ b/include/asm-x86/pgalloc_32.h @@ -80,8 +80,10 @@ set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT)); /* -* Pentium-II erratum A13: in PAE mode we explicitly have to flush -* the TLB via cr3 if the top-level pgd is changed... +* According to Intel App note TLBs, Paging-Structure Caches, +* and Their Invalidation, April 2007, document 317080-001, +* section 8.1: in PAE mode we explicitly have to flush the +* TLB via cr3 if the top-level pgd is changed... */ if (mm == current-active_mm) write_cr3(read_cr3()); diff --git a/include/asm-x86/pgtable-3level.h b/include/asm-x86/pgtable-3level.h --- a/include/asm-x86/pgtable-3level.h +++ b/include/asm-x86/pgtable-3level.h @@ -98,8 +98,10 @@ set_pud(pudp, __pud(0)); /* -* Pentium-II erratum A13: in PAE mode we explicitly have to flush -* the TLB via cr3 if the top-level pgd is changed... +* According to Intel App note TLBs, Paging-Structure Caches, +* and Their Invalidation, April 2007, document 317080-001, +* section 8.1: in PAE mode we explicitly have to flush the +* TLB via cr3 if the top-level pgd is changed... * * Make sure the pud entry we're updating is within the * current pgd to avoid unnecessary TLB flushes. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 4 of 4] x86: update reference for PAE tlb flushing
Remove bogus reference to "Pentium-II erratum A13" and point to the actual canonical source of information about what requirements x86 processors have for PAE pagetable updates. Signed-off-by: Jeremy Fitzhardinge <[EMAIL PROTECTED]> --- include/asm-x86/pgalloc_32.h |6 -- include/asm-x86/pgtable-3level.h |6 -- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/include/asm-x86/pgalloc_32.h b/include/asm-x86/pgalloc_32.h --- a/include/asm-x86/pgalloc_32.h +++ b/include/asm-x86/pgalloc_32.h @@ -87,8 +87,10 @@ static inline void pud_populate(struct m set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT)); /* -* Pentium-II erratum A13: in PAE mode we explicitly have to flush -* the TLB via cr3 if the top-level pgd is changed... +* According to Intel App note "TLBs, Paging-Structure Caches, +* and Their Invalidation", April 2007, document 317080-001, +* section 8.1: in PAE mode we explicitly have to flush the +* TLB via cr3 if the top-level pgd is changed... */ if (mm == current->active_mm) write_cr3(read_cr3()); diff --git a/include/asm-x86/pgtable-3level.h b/include/asm-x86/pgtable-3level.h --- a/include/asm-x86/pgtable-3level.h +++ b/include/asm-x86/pgtable-3level.h @@ -98,8 +98,10 @@ static inline void pud_clear(pud_t *pudp set_pud(pudp, __pud(0)); /* -* Pentium-II erratum A13: in PAE mode we explicitly have to flush -* the TLB via cr3 if the top-level pgd is changed... +* According to Intel App note "TLBs, Paging-Structure Caches, +* and Their Invalidation", April 2007, document 317080-001, +* section 8.1: in PAE mode we explicitly have to flush the +* TLB via cr3 if the top-level pgd is changed... * * Make sure the pud entry we're updating is within the * current pgd to avoid unnecessary TLB flushes. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 4 of 4] x86: update reference for PAE tlb flushing
Remove bogus reference to Pentium-II erratum A13 and point to the actual canonical source of information about what requirements x86 processors have for PAE pagetable updates. Signed-off-by: Jeremy Fitzhardinge [EMAIL PROTECTED] --- include/asm-x86/pgalloc_32.h |6 -- include/asm-x86/pgtable-3level.h |6 -- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/include/asm-x86/pgalloc_32.h b/include/asm-x86/pgalloc_32.h --- a/include/asm-x86/pgalloc_32.h +++ b/include/asm-x86/pgalloc_32.h @@ -87,8 +87,10 @@ static inline void pud_populate(struct m set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT)); /* -* Pentium-II erratum A13: in PAE mode we explicitly have to flush -* the TLB via cr3 if the top-level pgd is changed... +* According to Intel App note TLBs, Paging-Structure Caches, +* and Their Invalidation, April 2007, document 317080-001, +* section 8.1: in PAE mode we explicitly have to flush the +* TLB via cr3 if the top-level pgd is changed... */ if (mm == current-active_mm) write_cr3(read_cr3()); diff --git a/include/asm-x86/pgtable-3level.h b/include/asm-x86/pgtable-3level.h --- a/include/asm-x86/pgtable-3level.h +++ b/include/asm-x86/pgtable-3level.h @@ -98,8 +98,10 @@ static inline void pud_clear(pud_t *pudp set_pud(pudp, __pud(0)); /* -* Pentium-II erratum A13: in PAE mode we explicitly have to flush -* the TLB via cr3 if the top-level pgd is changed... +* According to Intel App note TLBs, Paging-Structure Caches, +* and Their Invalidation, April 2007, document 317080-001, +* section 8.1: in PAE mode we explicitly have to flush the +* TLB via cr3 if the top-level pgd is changed... * * Make sure the pud entry we're updating is within the * current pgd to avoid unnecessary TLB flushes. -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
