Re: [PATCH 4.14] x86/pae: use 64 bit atomic xchg function in native_ptep_get_and_clear

[Greg KH]

On Thu, Sep 13, 2018 at 11:56:11AM -0400, Jason Andryuk wrote:
> From: Juergen Gross 
> 
> commit b2d7a075a1ccef2fb321d595802190c8e9b39004 upstream
> 
> Using only 32-bit writes for the pte will result in an intermediate
> L1TF vulnerable PTE. When running as a Xen PV guest this will at once
> switch the guest to shadow mode resulting in a loss of performance.
> 
> Use arch_atomic64_xchg() instead which will perform the requested
> operation atomically with all 64 bits.
> 
> Some performance considerations according to:
> 
> https://software.intel.com/sites/default/files/managed/ad/dc/Intel-Xeon-Scalable-Processor-throughput-latency.pdf
> 
> The main number should be the latency, as there is no tight loop around
> native_ptep_get_and_clear().
> 
> "lock cmpxchg8b" has a latency of 20 cycles, while "lock xchg" (with a
> memory operand) isn't mentioned in that document. "lock xadd" (with xadd
> having 3 cycles less latency than xchg) has a latency of 11, so we can
> assume a latency of 14 for "lock xchg".
> 
> Signed-off-by: Juergen Gross 
> Reviewed-by: Thomas Gleixner 
> Reviewed-by: Jan Beulich 
> Tested-by: Jason Andryuk 
> Signed-off-by: Boris Ostrovsky 
> Atomic operations gained an arch_ prefix in commit
> 8bf705d130396e69c04cd8e6e010244ad2ce71f4
> s/arch_atomic64_xchg/atomic64_xchg/ for backport.
> Signed-off-by: Jason Andryuk 

Thanks for the fix, I've now queued it up everywhere and will push out
-rc2 versions of this.

greg k-h

[PATCH 4.14] x86/pae: use 64 bit atomic xchg function in native_ptep_get_and_clear

[Jason Andryuk]

From: Juergen Gross 

commit b2d7a075a1ccef2fb321d595802190c8e9b39004 upstream

Using only 32-bit writes for the pte will result in an intermediate
L1TF vulnerable PTE. When running as a Xen PV guest this will at once
switch the guest to shadow mode resulting in a loss of performance.

Use arch_atomic64_xchg() instead which will perform the requested
operation atomically with all 64 bits.

Some performance considerations according to:

https://software.intel.com/sites/default/files/managed/ad/dc/Intel-Xeon-Scalable-Processor-throughput-latency.pdf

The main number should be the latency, as there is no tight loop around
native_ptep_get_and_clear().

"lock cmpxchg8b" has a latency of 20 cycles, while "lock xchg" (with a
memory operand) isn't mentioned in that document. "lock xadd" (with xadd
having 3 cycles less latency than xchg) has a latency of 11, so we can
assume a latency of 14 for "lock xchg".

Signed-off-by: Juergen Gross 
Reviewed-by: Thomas Gleixner 
Reviewed-by: Jan Beulich 
Tested-by: Jason Andryuk 
Signed-off-by: Boris Ostrovsky 
Atomic operations gained an arch_ prefix in commit
8bf705d130396e69c04cd8e6e010244ad2ce71f4
s/arch_atomic64_xchg/atomic64_xchg/ for backport.
Signed-off-by: Jason Andryuk 
---
 arch/x86/include/asm/pgtable-3level.h | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/x86/include/asm/pgtable-3level.h 
b/arch/x86/include/asm/pgtable-3level.h
index 9dc19b4a2a87..c5d4931d1ef9 100644
--- a/arch/x86/include/asm/pgtable-3level.h
+++ b/arch/x86/include/asm/pgtable-3level.h
@@ -2,6 +2,8 @@
 #ifndef _ASM_X86_PGTABLE_3LEVEL_H
 #define _ASM_X86_PGTABLE_3LEVEL_H
 
+#include 
+
 /*
  * Intel Physical Address Extension (PAE) Mode - three-level page
  * tables on PPro+ CPUs.
@@ -147,10 +149,7 @@ static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
 {
pte_t res;
 
-   /* xchg acts as a barrier before the setting of the high bits */
-   res.pte_low = xchg(&ptep->pte_low, 0);
-   res.pte_high = ptep->pte_high;
-   ptep->pte_high = 0;
+   res.pte = (pteval_t)atomic64_xchg((atomic64_t *)ptep, 0);
 
return res;
 }
-- 
2.17.1