[PATCH 4.4 120/160] MIPS: Loongson-3: Fix CPU UART irq delivery problem
4.4-stable review patch. If anyone has any objections, please let me know.
--
[ Upstream commit d06f8a2f1befb5a3d0aa660ab1c05e9b744456ea ]
Masking/unmasking the CPU UART irq in CP0_Status (and redirecting it to
other CPUs) may cause interrupts be lost, especially in multi-package
machines (Package-0's UART irq cannot be delivered to others). So make
mask_loongson_irq() and unmask_loongson_irq() be no-ops.
The original problem (UART IRQ may deliver to any core) is also because
of masking/unmasking the CPU UART irq in CP0_Status. So it is safe to
remove all of the stuff.
Signed-off-by: Huacai Chen
Signed-off-by: Paul Burton
Patchwork: https://patchwork.linux-mips.org/patch/20433/
Cc: Ralf Baechle
Cc: James Hogan
Cc: linux-m...@linux-mips.org
Cc: Fuxin Zhang
Cc: Zhangjin Wu
Cc: Huacai Chen
Signed-off-by: Sasha Levin
---
arch/mips/loongson64/loongson-3/irq.c | 43 ++-
1 file changed, 3 insertions(+), 40 deletions(-)
diff --git a/arch/mips/loongson64/loongson-3/irq.c
b/arch/mips/loongson64/loongson-3/irq.c
index 0f75b6b3d218..53424f2a53f3 100644
--- a/arch/mips/loongson64/loongson-3/irq.c
+++ b/arch/mips/loongson64/loongson-3/irq.c
@@ -48,45 +48,8 @@ static struct irqaction cascade_irqaction = {
.name = "cascade",
};
-static inline void mask_loongson_irq(struct irq_data *d)
-{
- clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
- irq_disable_hazard();
-
- /* Workaround: UART IRQ may deliver to any core */
- if (d->irq == LOONGSON_UART_IRQ) {
- int cpu = smp_processor_id();
- int node_id = cpu_logical_map(cpu) /
loongson_sysconf.cores_per_node;
- int core_id = cpu_logical_map(cpu) %
loongson_sysconf.cores_per_node;
- u64 intenclr_addr = smp_group[node_id] |
- (u64)(_INT_ROUTER_INTENCLR);
- u64 introuter_lpc_addr = smp_group[node_id] |
- (u64)(_INT_ROUTER_LPC);
-
- *(volatile u32 *)intenclr_addr = 1 << 10;
- *(volatile u8 *)introuter_lpc_addr = 0x10 + (1
[PATCH 4.4 120/160] MIPS: Loongson-3: Fix CPU UART irq delivery problem
4.4-stable review patch. If anyone has any objections, please let me know.
--
[ Upstream commit d06f8a2f1befb5a3d0aa660ab1c05e9b744456ea ]
Masking/unmasking the CPU UART irq in CP0_Status (and redirecting it to
other CPUs) may cause interrupts be lost, especially in multi-package
machines (Package-0's UART irq cannot be delivered to others). So make
mask_loongson_irq() and unmask_loongson_irq() be no-ops.
The original problem (UART IRQ may deliver to any core) is also because
of masking/unmasking the CPU UART irq in CP0_Status. So it is safe to
remove all of the stuff.
Signed-off-by: Huacai Chen
Signed-off-by: Paul Burton
Patchwork: https://patchwork.linux-mips.org/patch/20433/
Cc: Ralf Baechle
Cc: James Hogan
Cc: linux-m...@linux-mips.org
Cc: Fuxin Zhang
Cc: Zhangjin Wu
Cc: Huacai Chen
Signed-off-by: Sasha Levin
---
arch/mips/loongson64/loongson-3/irq.c | 43 ++-
1 file changed, 3 insertions(+), 40 deletions(-)
diff --git a/arch/mips/loongson64/loongson-3/irq.c
b/arch/mips/loongson64/loongson-3/irq.c
index 0f75b6b3d218..53424f2a53f3 100644
--- a/arch/mips/loongson64/loongson-3/irq.c
+++ b/arch/mips/loongson64/loongson-3/irq.c
@@ -48,45 +48,8 @@ static struct irqaction cascade_irqaction = {
.name = "cascade",
};
-static inline void mask_loongson_irq(struct irq_data *d)
-{
- clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
- irq_disable_hazard();
-
- /* Workaround: UART IRQ may deliver to any core */
- if (d->irq == LOONGSON_UART_IRQ) {
- int cpu = smp_processor_id();
- int node_id = cpu_logical_map(cpu) /
loongson_sysconf.cores_per_node;
- int core_id = cpu_logical_map(cpu) %
loongson_sysconf.cores_per_node;
- u64 intenclr_addr = smp_group[node_id] |
- (u64)(_INT_ROUTER_INTENCLR);
- u64 introuter_lpc_addr = smp_group[node_id] |
- (u64)(_INT_ROUTER_LPC);
-
- *(volatile u32 *)intenclr_addr = 1 << 10;
- *(volatile u8 *)introuter_lpc_addr = 0x10 + (1
