Re: [PATCH 5/6] arm64: tegra: Add Tegra194 chip device tree
On Fri, Jan 12, 2018 at 1:22 AM, Mikko Perttunen wrote:
> On 11.01.2018 23:56, Rob Herring wrote:
>>
>> On Mon, Jan 08, 2018 at 06:54:37AM +0200, Mikko Perttunen wrote:
>>>
>>> Add the chip-level device tree, including binding headers, for the
>>> NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
>>> are initially available, enough to boot to UART console.
>>>
>>> Signed-off-by: Mikko Perttunen
>>> ---
>>> + interrupt-parent = <&gic>;
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> +
>>> + uarta: serial@310 {
>>
>>
>> These should all be under a bus node. Tegra failed to do this at the
>> start and we're still copy-n-pasting this mistake.
>>
>> Then you probably don't need 2 address and size cells for all the
>> peripherals.
>
>
> So I should create one big simple-bus node and put everything with an
> address apart from /memory (and maybe /sysram) inside it?
Yes. Though you can have multiple buses if that makes sense. Things
like fixed clocks, gpio-leds, etc. (typically board level) that don't
have any bus should stay at the top level.
Rob
Re: [PATCH 5/6] arm64: tegra: Add Tegra194 chip device tree
On 11.01.2018 23:56, Rob Herring wrote:
On Mon, Jan 08, 2018 at 06:54:37AM +0200, Mikko Perttunen wrote:
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 334 +
include/dt-bindings/clock/tegra194-clock.h | 59 +
include/dt-bindings/gpio/tegra194-gpio.h | 59 +
include/dt-bindings/reset/tegra194-reset.h | 40
4 files changed, 492 insertions(+)
create mode 100644 arch/arm64/boot/dts/nvidia/tegra194.dtsi
create mode 100644 include/dt-bindings/clock/tegra194-clock.h
create mode 100644 include/dt-bindings/gpio/tegra194-gpio.h
create mode 100644 include/dt-bindings/reset/tegra194-reset.h
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
new file mode 100644
index ..51eff420816d
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -0,0 +1,334 @@
+// SPDX-License-Identifier: GPL-2.0
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "nvidia,tegra194";
Documented?
Ah, wasn't aware these needed to be documented as well. Will add in v2.
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ uarta: serial@310 {
These should all be under a bus node. Tegra failed to do this at the
start and we're still copy-n-pasting this mistake.
Then you probably don't need 2 address and size cells for all the
peripherals.
So I should create one big simple-bus node and put everything with an
address apart from /memory (and maybe /sysram) inside it?
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0310 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTA>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTA>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartb: serial@311 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0311 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTB>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTB>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartd: serial@313 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0313 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTD>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTD>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uarte: serial@314 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0314 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTE>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTE>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartf: serial@315 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0315 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTF>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTF>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ gen1_i2c: i2c@316 {
+ compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x0316 0x0 0x1>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA194_CLK_I2C1>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA194_RESET_I2C1>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ uarth: serial@317 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0317 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTH>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTH>;
+ reset-names = "serial";
+ status = "disab
Re: [PATCH 5/6] arm64: tegra: Add Tegra194 chip device tree
On Mon, Jan 08, 2018 at 06:54:37AM +0200, Mikko Perttunen wrote:
> Add the chip-level device tree, including binding headers, for the
> NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
> are initially available, enough to boot to UART console.
>
> Signed-off-by: Mikko Perttunen
> ---
> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 334
> +
> include/dt-bindings/clock/tegra194-clock.h | 59 +
> include/dt-bindings/gpio/tegra194-gpio.h | 59 +
> include/dt-bindings/reset/tegra194-reset.h | 40
> 4 files changed, 492 insertions(+)
> create mode 100644 arch/arm64/boot/dts/nvidia/tegra194.dtsi
> create mode 100644 include/dt-bindings/clock/tegra194-clock.h
> create mode 100644 include/dt-bindings/gpio/tegra194-gpio.h
> create mode 100644 include/dt-bindings/reset/tegra194-reset.h
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> new file mode 100644
> index ..51eff420816d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -0,0 +1,334 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/ {
> + compatible = "nvidia,tegra194";
Documented?
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + uarta: serial@310 {
These should all be under a bus node. Tegra failed to do this at the
start and we're still copy-n-pasting this mistake.
Then you probably don't need 2 address and size cells for all the
peripherals.
> + compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
> + reg = <0x0 0x0310 0x0 0x40>;
> + reg-shift = <2>;
> + interrupts = ;
> + clocks = <&bpmp TEGRA194_CLK_UARTA>;
> + clock-names = "serial";
> + resets = <&bpmp TEGRA194_RESET_UARTA>;
> + reset-names = "serial";
> + status = "disabled";
> + };
> +
> + uartb: serial@311 {
> + compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
> + reg = <0x0 0x0311 0x0 0x40>;
> + reg-shift = <2>;
> + interrupts = ;
> + clocks = <&bpmp TEGRA194_CLK_UARTB>;
> + clock-names = "serial";
> + resets = <&bpmp TEGRA194_RESET_UARTB>;
> + reset-names = "serial";
> + status = "disabled";
> + };
> +
> + uartd: serial@313 {
> + compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
> + reg = <0x0 0x0313 0x0 0x40>;
> + reg-shift = <2>;
> + interrupts = ;
> + clocks = <&bpmp TEGRA194_CLK_UARTD>;
> + clock-names = "serial";
> + resets = <&bpmp TEGRA194_RESET_UARTD>;
> + reset-names = "serial";
> + status = "disabled";
> + };
> +
> + uarte: serial@314 {
> + compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
> + reg = <0x0 0x0314 0x0 0x40>;
> + reg-shift = <2>;
> + interrupts = ;
> + clocks = <&bpmp TEGRA194_CLK_UARTE>;
> + clock-names = "serial";
> + resets = <&bpmp TEGRA194_RESET_UARTE>;
> + reset-names = "serial";
> + status = "disabled";
> + };
> +
> + uartf: serial@315 {
> + compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
> + reg = <0x0 0x0315 0x0 0x40>;
> + reg-shift = <2>;
> + interrupts = ;
> + clocks = <&bpmp TEGRA194_CLK_UARTF>;
> + clock-names = "serial";
> + resets = <&bpmp TEGRA194_RESET_UARTF>;
> + reset-names = "serial";
> + status = "disabled";
> + };
> +
> + gen1_i2c: i2c@316 {
> + compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
> + reg = <0x0 0x0316 0x0 0x1>;
> + interrupts = ;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&bpmp TEGRA194_CLK_I2C1>;
> + clock-names = "div-clk";
> + resets = <&bpmp TEGRA194_RESET_I2C1>;
> + reset-names = "i2c";
> + status = "disabled";
> + };
> +
> + uarth: serial@317 {
> + compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
> + reg = <0x0 0x0317 0x0 0x40>;
> + reg-shift = <2>;
> + interrupts = ;
> + clocks = <&bpmp TEGRA194_CLK_UARTH>;
> + clock-names = "serial";
> + resets = <&bpmp TEGRA194_RESET_UARTH>;
> + reset-names = "serial";
> + status = "disabled";
> + };
> +
> + cam_i2c: i2c@318 {
> + compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
> + reg = <0x0 0x0318 0x0 0x1
[PATCH 5/6] arm64: tegra: Add Tegra194 chip device tree
Add the chip-level device tree, including binding headers, for the
NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
are initially available, enough to boot to UART console.
Signed-off-by: Mikko Perttunen
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 334 +
include/dt-bindings/clock/tegra194-clock.h | 59 +
include/dt-bindings/gpio/tegra194-gpio.h | 59 +
include/dt-bindings/reset/tegra194-reset.h | 40
4 files changed, 492 insertions(+)
create mode 100644 arch/arm64/boot/dts/nvidia/tegra194.dtsi
create mode 100644 include/dt-bindings/clock/tegra194-clock.h
create mode 100644 include/dt-bindings/gpio/tegra194-gpio.h
create mode 100644 include/dt-bindings/reset/tegra194-reset.h
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
new file mode 100644
index ..51eff420816d
--- /dev/null
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -0,0 +1,334 @@
+// SPDX-License-Identifier: GPL-2.0
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "nvidia,tegra194";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ uarta: serial@310 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0310 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTA>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTA>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartb: serial@311 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0311 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTB>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTB>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartd: serial@313 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0313 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTD>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTD>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uarte: serial@314 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0314 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTE>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTE>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ uartf: serial@315 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0315 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTF>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTF>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ gen1_i2c: i2c@316 {
+ compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x0316 0x0 0x1>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA194_CLK_I2C1>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA194_RESET_I2C1>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ uarth: serial@317 {
+ compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
+ reg = <0x0 0x0317 0x0 0x40>;
+ reg-shift = <2>;
+ interrupts = ;
+ clocks = <&bpmp TEGRA194_CLK_UARTH>;
+ clock-names = "serial";
+ resets = <&bpmp TEGRA194_RESET_UARTH>;
+ reset-names = "serial";
+ status = "disabled";
+ };
+
+ cam_i2c: i2c@318 {
+ compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
+ reg = <0x0 0x0318 0x0 0x1>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&bpmp TEGRA194_CLK_I2C3>;
+ clock-names = "div-clk";
+ resets = <&bpmp TEGRA194_RESET_I2C3>;
+ reset-names = "i2c";
+ status = "disabled";
+ };
+
+ /* shares pads
