[PATCH 5/7] phy: qcom-qmp: Add support for IPQ8074

[Varadarajan Narayanan]

Add definitions required to enable QMP phy support for IPQ8074.

Signed-off-by: smuthayy 
Signed-off-by: Varadarajan Narayanan 
---
 drivers/phy/qualcomm/phy-qcom-qmp.c | 135 
 1 file changed, 135 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c 
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 000ad1c..9019f66 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -59,6 +59,7 @@
 #define QSERDES_COM_PLL_RCTRL_MODE10x088
 #define QSERDES_COM_PLL_CCTRL_MODE00x090
 #define QSERDES_COM_PLL_CCTRL_MODE10x094
+#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM0x0a8
 #define QSERDES_COM_SYSCLK_EN_SEL  0x0ac
 #define QSERDES_COM_RESETSM_CNTRL  0x0b4
 #define QSERDES_COM_RESTRIM_CTRL   0x0bc
@@ -143,6 +144,11 @@
 #define QPHY_LOCK_DETECT_CONFIG3   0x88
 #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK   0xa0
 #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
+#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB  0x1A8
+#define QPHY_OSC_DTCT_ACTIONS  0x1AC
+#define QPHY_RX_SIGDET_LVL 0x1D8
+#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB   0x1DC
+#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB   0x1E0
 
 /* QPHY_SW_RESET bit */
 #define SW_RESET   BIT(0)
@@ -224,6 +230,17 @@ enum qphy_reg_layout {
[QPHY_PCS_READY_STATUS] = 0x174,
 };
 
+static const unsigned int ipq8074_pciephy_regs_layout[] = {
+   [QPHY_COM_SW_RESET] = 0x800,
+   [QPHY_COM_POWER_DOWN_CONTROL]   = 0x804,
+   [QPHY_COM_START_CONTROL]= 0x808,
+   [QPHY_COM_PCS_READY_STATUS] = QPHY_REG_INVAL,
+   [QPHY_PLL_LOCK_CHK_DLY_TIME]= 0xa8,
+   [QPHY_SW_RESET] = 0x00,
+   [QPHY_START_CTRL]   = 0x08,
+   [QPHY_PCS_READY_STATUS] = 0x174,
+};
+
 static const unsigned int usb3phy_regs_layout[] = {
[QPHY_FLL_CNTRL1]   = 0xc0,
[QPHY_FLL_CNTRL2]   = 0xc4,
@@ -582,6 +599,121 @@ static inline void qphy_clrbits(void __iomem *base, u32 
offset, u32 val)
.mask_pcs_ready = PHYSTATUS,
 };
 
+static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
+   QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
+   QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
+   QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
+   QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
+   QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
+   QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+   QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+   QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+   QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
+   QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
+};
+
+static const struct 

[PATCH 5/7] phy: qcom-qmp: Add support for IPQ8074

[Varadarajan Narayanan]

Add definitions required to enable QMP phy support for IPQ8074.

Signed-off-by: smuthayy 
Signed-off-by: Varadarajan Narayanan 
---
 drivers/phy/qualcomm/phy-qcom-qmp.c | 135 
 1 file changed, 135 insertions(+)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c 
b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 000ad1c..9019f66 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -59,6 +59,7 @@
 #define QSERDES_COM_PLL_RCTRL_MODE10x088
 #define QSERDES_COM_PLL_CCTRL_MODE00x090
 #define QSERDES_COM_PLL_CCTRL_MODE10x094
+#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM0x0a8
 #define QSERDES_COM_SYSCLK_EN_SEL  0x0ac
 #define QSERDES_COM_RESETSM_CNTRL  0x0b4
 #define QSERDES_COM_RESTRIM_CTRL   0x0bc
@@ -143,6 +144,11 @@
 #define QPHY_LOCK_DETECT_CONFIG3   0x88
 #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK   0xa0
 #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
+#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB  0x1A8
+#define QPHY_OSC_DTCT_ACTIONS  0x1AC
+#define QPHY_RX_SIGDET_LVL 0x1D8
+#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB   0x1DC
+#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB   0x1E0
 
 /* QPHY_SW_RESET bit */
 #define SW_RESET   BIT(0)
@@ -224,6 +230,17 @@ enum qphy_reg_layout {
[QPHY_PCS_READY_STATUS] = 0x174,
 };
 
+static const unsigned int ipq8074_pciephy_regs_layout[] = {
+   [QPHY_COM_SW_RESET] = 0x800,
+   [QPHY_COM_POWER_DOWN_CONTROL]   = 0x804,
+   [QPHY_COM_START_CONTROL]= 0x808,
+   [QPHY_COM_PCS_READY_STATUS] = QPHY_REG_INVAL,
+   [QPHY_PLL_LOCK_CHK_DLY_TIME]= 0xa8,
+   [QPHY_SW_RESET] = 0x00,
+   [QPHY_START_CTRL]   = 0x08,
+   [QPHY_PCS_READY_STATUS] = 0x174,
+};
+
 static const unsigned int usb3phy_regs_layout[] = {
[QPHY_FLL_CNTRL1]   = 0xc0,
[QPHY_FLL_CNTRL2]   = 0xc4,
@@ -582,6 +599,121 @@ static inline void qphy_clrbits(void __iomem *base, u32 
offset, u32 val)
.mask_pcs_ready = PHYSTATUS,
 };
 
+static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
+   QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
+   QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0x1f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
+   QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
+   QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
+   QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
+   QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
+   QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
+   QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
+   QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
+   QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
+   QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0xa),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
+   QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
+   QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
+   QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x7),
+};
+
+static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
+