[PATCH 6/7] arm: zynq: Migrate platform to clock controller
Migrate the Zynq platform and its drivers to use the new clock
controller driver.
Signed-off-by: Soren Brinkmann
Cc: John Stultz
Cc: Thomas Gleixner
Cc: Greg Kroah-Hartman
Cc: Jiri Slaby
Cc: linux-ser...@vger.kernel.org
---
arch/arm/boot/dts/zynq-7000.dtsi| 71 ---
arch/arm/boot/dts/zynq-zc702.dts| 4 --
arch/arm/mach-zynq/slcr.c | 2 +-
drivers/clk/Makefile| 2 +-
drivers/clk/zynq/Makefile | 3 ++
drivers/clocksource/cadence_ttc_timer.c | 23 +++--
drivers/tty/serial/xilinx_uartps.c | 85 ++---
include/linux/clk/zynq.h| 8 +++-
8 files changed, 118 insertions(+), 80 deletions(-)
create mode 100644 drivers/clk/zynq/Makefile
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 2a1df1b..5337554 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -42,16 +42,18 @@
uart0: uart@e000 {
compatible = "xlnx,xuartps";
+ clocks = < 23>, < 40>;
+ clock-names = "ref_clk", "aper_clk";
reg = <0xE000 0x1000>;
interrupts = <0 27 4>;
- clocks = <_clk 0>;
};
uart1: uart@e0001000 {
compatible = "xlnx,xuartps";
+ clocks = < 24>, < 41>;
+ clock-names = "ref_clk", "aper_clk";
reg = <0xE0001000 0x1000>;
interrupts = <0 50 4>;
- clocks = <_clk 1>;
};
slcr: slcr@f800 {
@@ -62,50 +64,21 @@
#address-cells = <1>;
#size-cells = <0>;
- ps_clk: ps_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- /* clock-frequency set in
board-specific file */
- clock-output-names = "ps_clk";
- };
- armpll: armpll {
- #clock-cells = <0>;
- compatible = "xlnx,zynq-pll";
- clocks = <_clk>;
- reg = <0x100 0x110>;
- clock-output-names = "armpll";
- };
- ddrpll: ddrpll {
- #clock-cells = <0>;
- compatible = "xlnx,zynq-pll";
- clocks = <_clk>;
- reg = <0x104 0x114>;
- clock-output-names = "ddrpll";
- };
- iopll: iopll {
- #clock-cells = <0>;
- compatible = "xlnx,zynq-pll";
- clocks = <_clk>;
- reg = <0x108 0x118>;
- clock-output-names = "iopll";
- };
- uart_clk: uart_clk {
- #clock-cells = <1>;
- compatible = "xlnx,zynq-periph-clock";
- clocks = < >;
- reg = <0x154>;
- clock-output-names = "uart0_ref_clk",
-"uart1_ref_clk";
- };
- cpu_clk: cpu_clk {
+ clkc: clkc {
#clock-cells = <1>;
- compatible = "xlnx,zynq-cpu-clock";
- clocks = < >;
- reg = <0x120 0x1C4>;
- clock-output-names = "cpu_6x4x",
-"cpu_3x2x",
-"cpu_2x",
-"cpu_1x";
+ compatible = "xlnx,ps7-clkc";
+ ps-clk-frequency = <>;
+ clock-output-names = "armpll",
"ddrpll", "iopll", "cpu_6or4x",
+ "cpu_3or2x", "cpu_2x",
"cpu_1x", "ddr2x", "ddr3x",
+
[PATCH 6/7] arm: zynq: Migrate platform to clock controller
Migrate the Zynq platform and its drivers to use the new clock
controller driver.
Signed-off-by: Soren Brinkmann soren.brinkm...@xilinx.com
Cc: John Stultz john.stu...@linaro.org
Cc: Thomas Gleixner t...@linutronix.de
Cc: Greg Kroah-Hartman gre...@linuxfoundation.org
Cc: Jiri Slaby jsl...@suse.cz
Cc: linux-ser...@vger.kernel.org
---
arch/arm/boot/dts/zynq-7000.dtsi| 71 ---
arch/arm/boot/dts/zynq-zc702.dts| 4 --
arch/arm/mach-zynq/slcr.c | 2 +-
drivers/clk/Makefile| 2 +-
drivers/clk/zynq/Makefile | 3 ++
drivers/clocksource/cadence_ttc_timer.c | 23 +++--
drivers/tty/serial/xilinx_uartps.c | 85 ++---
include/linux/clk/zynq.h| 8 +++-
8 files changed, 118 insertions(+), 80 deletions(-)
create mode 100644 drivers/clk/zynq/Makefile
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 2a1df1b..5337554 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -42,16 +42,18 @@
uart0: uart@e000 {
compatible = xlnx,xuartps;
+ clocks = clkc 23, clkc 40;
+ clock-names = ref_clk, aper_clk;
reg = 0xE000 0x1000;
interrupts = 0 27 4;
- clocks = uart_clk 0;
};
uart1: uart@e0001000 {
compatible = xlnx,xuartps;
+ clocks = clkc 24, clkc 41;
+ clock-names = ref_clk, aper_clk;
reg = 0xE0001000 0x1000;
interrupts = 0 50 4;
- clocks = uart_clk 1;
};
slcr: slcr@f800 {
@@ -62,50 +64,21 @@
#address-cells = 1;
#size-cells = 0;
- ps_clk: ps_clk {
- #clock-cells = 0;
- compatible = fixed-clock;
- /* clock-frequency set in
board-specific file */
- clock-output-names = ps_clk;
- };
- armpll: armpll {
- #clock-cells = 0;
- compatible = xlnx,zynq-pll;
- clocks = ps_clk;
- reg = 0x100 0x110;
- clock-output-names = armpll;
- };
- ddrpll: ddrpll {
- #clock-cells = 0;
- compatible = xlnx,zynq-pll;
- clocks = ps_clk;
- reg = 0x104 0x114;
- clock-output-names = ddrpll;
- };
- iopll: iopll {
- #clock-cells = 0;
- compatible = xlnx,zynq-pll;
- clocks = ps_clk;
- reg = 0x108 0x118;
- clock-output-names = iopll;
- };
- uart_clk: uart_clk {
- #clock-cells = 1;
- compatible = xlnx,zynq-periph-clock;
- clocks = iopll armpll ddrpll;
- reg = 0x154;
- clock-output-names = uart0_ref_clk,
-uart1_ref_clk;
- };
- cpu_clk: cpu_clk {
+ clkc: clkc {
#clock-cells = 1;
- compatible = xlnx,zynq-cpu-clock;
- clocks = iopll armpll ddrpll;
- reg = 0x120 0x1C4;
- clock-output-names = cpu_6x4x,
-cpu_3x2x,
-cpu_2x,
-cpu_1x;
+ compatible = xlnx,ps7-clkc;
+ ps-clk-frequency = ;
+ clock-output-names = armpll,
ddrpll, iopll, cpu_6or4x,
+ cpu_3or2x, cpu_2x,
cpu_1x, ddr2x, ddr3x,
+
