Add support for the IPQ8074 PCIe controller. IPQ8074 supports Gen 1/2, one
lane, two PCIe root complex with support for MSI and legacy interrupts, and
it conforms to PCI Express Base 2.1 specification.
Signed-off-by: Varadarajan Narayanan
---
.../devicetree/bindings/pci/qcom,pcie.txt | 67 ++
1 file changed, 67 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 9d418b7..643bcc2 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -9,6 +9,7 @@
- "qcom,pcie-apq8084" for apq8084
- "qcom,pcie-msm8996" for msm8996 or apq8096
- "qcom,pcie-ipq4019" for ipq4019
+ - "qcom,pcie-ipq8074" for ipq8074
- reg:
Usage: required
@@ -261,3 +262,69 @@
pinctrl-0 = <&pcie0_pins_default>;
pinctrl-names = "default";
};
+
+* Example for ipq8074
+ pcie0: pci@2000 {
+ compatible = "qcom,pcie-ipq8074";
+ reg = <0x2000 0xf1d
+ 0x2F20 0xa8
+ 0x8 0x2000
+ 0x2010 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pciephy_0>;
+ phy-names = "pciephy";
+
+ ranges = <0x8100 0 0x2020 0x2020
+ 0 0x0010 /* downstream I/O */
+ 0x8200 0 0x2030 0x2030
+ 0 0x00d0>; /* non-prefetchable memory */
+
+ interrupts = <0 52 0>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 75
+IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 78
+IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 79
+IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 83
+IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks =<&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+ <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_PCIE0_AUX_CLK>;
+ clock-names = "sys_noc",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+<&gcc GCC_PCIE0_SLEEP_ARES>,
+<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+<&gcc GCC_PCIE0_AHB_ARES>,
+<&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky";
+
+ perst-gpio = <&tlmm 58 1>;
+ status = "disabled";
+ };
--
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