Re: [PATCH 8/9] clk: sunxi-ng: Add A31/A31s clocks

[Maxime Ripard]

On Tue, Jul 26, 2016 at 03:04:30PM +0800, Chen-Yu Tsai wrote:
> Add a new style driver for the clock control unit in Allwinner A31/A31s.
> 
> A few clocks are still missing:
> 
> - EMAC clock
> 
> Signed-off-by: Chen-Yu Tsai 

Looks good to me, aside from the comment made by Jean-Francois.

I guess I'd prefer to have the SoC names in the define, just in case
we need to introduce support for another SoC, but this can always be
done later.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [PATCH 8/9] clk: sunxi-ng: Add A31/A31s clocks

[Maxime Ripard]

On Tue, Jul 26, 2016 at 03:04:30PM +0800, Chen-Yu Tsai wrote:
> Add a new style driver for the clock control unit in Allwinner A31/A31s.
> 
> A few clocks are still missing:
> 
> - EMAC clock
> 
> Signed-off-by: Chen-Yu Tsai 

Looks good to me, aside from the comment made by Jean-Francois.

I guess I'd prefer to have the SoC names in the define, just in case
we need to introduce support for another SoC, but this can always be
done later.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com


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Re: [PATCH 8/9] clk: sunxi-ng: Add A31/A31s clocks

[Rob Herring]

On Tue, Jul 26, 2016 at 03:04:30PM +0800, Chen-Yu Tsai wrote:
> Add a new style driver for the clock control unit in Allwinner A31/A31s.
> 
> A few clocks are still missing:
> 
> - EMAC clock
> 
> Signed-off-by: Chen-Yu Tsai 
> ---
>  .../devicetree/bindings/clock/sunxi-ccu.txt|3 +-

Acked-by: Rob Herring 

>  drivers/clk/sunxi-ng/Kconfig   |   10 +
>  drivers/clk/sunxi-ng/Makefile  |1 +
>  drivers/clk/sunxi-ng/ccu-sun6i-a31.c   | 1230 
> 
>  drivers/clk/sunxi-ng/ccu-sun6i-a31.h   |   72 ++
>  include/dt-bindings/clock/sun6i-a31-ccu.h  |  187 +++
>  include/dt-bindings/reset/sun6i-a31-ccu.h  |  106 ++
>  7 files changed, 1608 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-a31.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-a31.h
>  create mode 100644 include/dt-bindings/clock/sun6i-a31-ccu.h
>  create mode 100644 include/dt-bindings/reset/sun6i-a31-ccu.h

Re: [PATCH 8/9] clk: sunxi-ng: Add A31/A31s clocks

[Rob Herring]

On Tue, Jul 26, 2016 at 03:04:30PM +0800, Chen-Yu Tsai wrote:
> Add a new style driver for the clock control unit in Allwinner A31/A31s.
> 
> A few clocks are still missing:
> 
> - EMAC clock
> 
> Signed-off-by: Chen-Yu Tsai 
> ---
>  .../devicetree/bindings/clock/sunxi-ccu.txt|3 +-

Acked-by: Rob Herring 

>  drivers/clk/sunxi-ng/Kconfig   |   10 +
>  drivers/clk/sunxi-ng/Makefile  |1 +
>  drivers/clk/sunxi-ng/ccu-sun6i-a31.c   | 1230 
> 
>  drivers/clk/sunxi-ng/ccu-sun6i-a31.h   |   72 ++
>  include/dt-bindings/clock/sun6i-a31-ccu.h  |  187 +++
>  include/dt-bindings/reset/sun6i-a31-ccu.h  |  106 ++
>  7 files changed, 1608 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-a31.c
>  create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-a31.h
>  create mode 100644 include/dt-bindings/clock/sun6i-a31-ccu.h
>  create mode 100644 include/dt-bindings/reset/sun6i-a31-ccu.h

Re: [PATCH 8/9] clk: sunxi-ng: Add A31/A31s clocks

[Jean-Francois Moine]

On Tue, 26 Jul 2016 15:04:30 +0800
Chen-Yu Tsai  wrote:

> +static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
> + { .index = 0, .div = 750, },
> + { .index = 3, .div = 4, },
> + { .index = 4, .div = 4, },
> +};

No end of table.

-- 
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef |   http://moinejf.free.fr/

Re: [PATCH 8/9] clk: sunxi-ng: Add A31/A31s clocks

[Jean-Francois Moine]

On Tue, 26 Jul 2016 15:04:30 +0800
Chen-Yu Tsai  wrote:

> +static const struct ccu_mux_fixed_prediv clk_out_predivs[] = {
> + { .index = 0, .div = 750, },
> + { .index = 3, .div = 4, },
> + { .index = 4, .div = 4, },
> +};

No end of table.

-- 
Ken ar c'hentañ | ** Breizh ha Linux atav! **
Jef |   http://moinejf.free.fr/

[PATCH 8/9] clk: sunxi-ng: Add A31/A31s clocks

[Chen-Yu Tsai]

Add a new style driver for the clock control unit in Allwinner A31/A31s.

A few clocks are still missing:

- EMAC clock

Signed-off-by: Chen-Yu Tsai 
---
 .../devicetree/bindings/clock/sunxi-ccu.txt|3 +-
 drivers/clk/sunxi-ng/Kconfig   |   10 +
 drivers/clk/sunxi-ng/Makefile  |1 +
 drivers/clk/sunxi-ng/ccu-sun6i-a31.c   | 1230 
 drivers/clk/sunxi-ng/ccu-sun6i-a31.h   |   72 ++
 include/dt-bindings/clock/sun6i-a31-ccu.h  |  187 +++
 include/dt-bindings/reset/sun6i-a31-ccu.h  |  106 ++
 7 files changed, 1608 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-a31.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-a31.h
 create mode 100644 include/dt-bindings/clock/sun6i-a31-ccu.h
 create mode 100644 include/dt-bindings/reset/sun6i-a31-ccu.h

diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt 
b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index cb91507ffb1e..eac458720b28 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -2,7 +2,8 @@ Allwinner Clock Control Unit Binding
 
 
 Required properties :
-- compatible: must contain one of the following compatible:
+- compatible: must contain one of the following compatibles:
+   - "allwinner,sun6i-a31-ccu"
- "allwinner,sun8i-h3-ccu"
 
 - reg: Must contain the registers base address and length
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 2afcbd39e41e..a1dee861474c 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -51,6 +51,16 @@ config SUNXI_CCU_MP
 
 # SoC Drivers
 
+config SUN6I_A31_CCU
+   bool "Support for the Allwinner A31/A31s CCU"
+   select SUNXI_CCU_DIV
+   select SUNXI_CCU_NK
+   select SUNXI_CCU_NKM
+   select SUNXI_CCU_NM
+   select SUNXI_CCU_MP
+   select SUNXI_CCU_PHASE
+   default MACH_SUN6I
+
 config SUN8I_H3_CCU
bool "Support for the Allwinner H3 CCU"
select SUNXI_CCU_DIV
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 633ce642ffae..261438b00215 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -17,4 +17,5 @@ obj-$(CONFIG_SUNXI_CCU_NM)+= ccu_nm.o
 obj-$(CONFIG_SUNXI_CCU_MP) += ccu_mp.o
 
 # SoC support
+obj-$(CONFIG_SUN6I_A31_CCU)+= ccu-sun6i-a31.o
 obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c 
b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
new file mode 100644
index ..ee1208aa9c0a
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -0,0 +1,1230 @@
+/*
+ * Copyright (c) 2016 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai 
+ *
+ * Based on ccu-sun8i-h3.c by Maxime Ripard.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_mux.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun6i-a31.h"
+
+static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
+"osc24M", 0x000,
+8, 5,  /* N */
+4, 2,  /* K */
+0, 2,  /* M */
+BIT(31),   /* gate */
+BIT(28),   /* lock */
+0);
+
+/*
+ * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+ * the base (2x, 4x and 8x), and one variable divider (the one true
+ * pll audio).
+ *
+ * We don't have any need for the variable divider for now, so we just
+ * hardcode it to match with the clock names
+ */
+#define SUN6I_A31_PLL_AUDIO_REG0x008
+
+static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
+  "osc24M", 0x008,
+  8, 7,/* N */
+  0, 5,/* M */
+  BIT(31), /* gate */
+  BIT(28), /* lock */
+  0);
+
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, 

[PATCH 8/9] clk: sunxi-ng: Add A31/A31s clocks

[Chen-Yu Tsai]

Add a new style driver for the clock control unit in Allwinner A31/A31s.

A few clocks are still missing:

- EMAC clock

Signed-off-by: Chen-Yu Tsai 
---
 .../devicetree/bindings/clock/sunxi-ccu.txt|3 +-
 drivers/clk/sunxi-ng/Kconfig   |   10 +
 drivers/clk/sunxi-ng/Makefile  |1 +
 drivers/clk/sunxi-ng/ccu-sun6i-a31.c   | 1230 
 drivers/clk/sunxi-ng/ccu-sun6i-a31.h   |   72 ++
 include/dt-bindings/clock/sun6i-a31-ccu.h  |  187 +++
 include/dt-bindings/reset/sun6i-a31-ccu.h  |  106 ++
 7 files changed, 1608 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-a31.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun6i-a31.h
 create mode 100644 include/dt-bindings/clock/sun6i-a31-ccu.h
 create mode 100644 include/dt-bindings/reset/sun6i-a31-ccu.h

diff --git a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt 
b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
index cb91507ffb1e..eac458720b28 100644
--- a/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi-ccu.txt
@@ -2,7 +2,8 @@ Allwinner Clock Control Unit Binding
 
 
 Required properties :
-- compatible: must contain one of the following compatible:
+- compatible: must contain one of the following compatibles:
+   - "allwinner,sun6i-a31-ccu"
- "allwinner,sun8i-h3-ccu"
 
 - reg: Must contain the registers base address and length
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 2afcbd39e41e..a1dee861474c 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -51,6 +51,16 @@ config SUNXI_CCU_MP
 
 # SoC Drivers
 
+config SUN6I_A31_CCU
+   bool "Support for the Allwinner A31/A31s CCU"
+   select SUNXI_CCU_DIV
+   select SUNXI_CCU_NK
+   select SUNXI_CCU_NKM
+   select SUNXI_CCU_NM
+   select SUNXI_CCU_MP
+   select SUNXI_CCU_PHASE
+   default MACH_SUN6I
+
 config SUN8I_H3_CCU
bool "Support for the Allwinner H3 CCU"
select SUNXI_CCU_DIV
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 633ce642ffae..261438b00215 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -17,4 +17,5 @@ obj-$(CONFIG_SUNXI_CCU_NM)+= ccu_nm.o
 obj-$(CONFIG_SUNXI_CCU_MP) += ccu_mp.o
 
 # SoC support
+obj-$(CONFIG_SUN6I_A31_CCU)+= ccu-sun6i-a31.o
 obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c 
b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
new file mode 100644
index ..ee1208aa9c0a
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c
@@ -0,0 +1,1230 @@
+/*
+ * Copyright (c) 2016 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai 
+ *
+ * Based on ccu-sun8i-h3.c by Maxime Ripard.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_mux.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun6i-a31.h"
+
+static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
+"osc24M", 0x000,
+8, 5,  /* N */
+4, 2,  /* K */
+0, 2,  /* M */
+BIT(31),   /* gate */
+BIT(28),   /* lock */
+0);
+
+/*
+ * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+ * the base (2x, 4x and 8x), and one variable divider (the one true
+ * pll audio).
+ *
+ * We don't have any need for the variable divider for now, so we just
+ * hardcode it to match with the clock names
+ */
+#define SUN6I_A31_PLL_AUDIO_REG0x008
+
+static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
+  "osc24M", 0x008,
+  8, 7,/* N */
+  0, 5,/* M */
+  BIT(31), /* gate */
+  BIT(28), /* lock */
+  0);
+
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
+