Re: [PATCH 8/9] platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake
Please ignore the typo in my previous email and use this tag instead. Acked-by: Rajneesh Bhardwaj On Wed, Apr 7, 2021 at 11:48 AM Rajneesh Bhardwaj wrote: > > Acked-by: Rajneesh Bhardwaj > > On Wed, Mar 31, 2021 at 11:06 PM David E. Box > wrote: > > > > From: Gayatri Kammela > > > > Just like Ice Lake, Tiger Lake uses Cannon Lake's LTR information > > and supports a few additional registers. Hence add the LTR registers > > specific to Tiger Lake to the cnp_ltr_show_map[]. > > > > Also adjust the number of LTR IPs for Tiger Lake to the correct amount. > > > > Signed-off-by: Gayatri Kammela > > Signed-off-by: David E. Box > > --- > > drivers/platform/x86/intel_pmc_core.c | 2 ++ > > drivers/platform/x86/intel_pmc_core.h | 4 +++- > > 2 files changed, 5 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/platform/x86/intel_pmc_core.c > > b/drivers/platform/x86/intel_pmc_core.c > > index 458c0056e7a1..9168062c927e 100644 > > --- a/drivers/platform/x86/intel_pmc_core.c > > +++ b/drivers/platform/x86/intel_pmc_core.c > > @@ -383,6 +383,8 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = { > > * a list of core SoCs using this. > > */ > > {"WIGIG", ICL_PMC_LTR_WIGIG}, > > + {"THC0",TGL_PMC_LTR_THC0}, > > + {"THC1",TGL_PMC_LTR_THC1}, > > /* Below two cannot be used for LTR_IGNORE */ > > {"CURRENT_PLATFORM",CNP_PMC_LTR_CUR_PLT}, > > {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, > > diff --git a/drivers/platform/x86/intel_pmc_core.h > > b/drivers/platform/x86/intel_pmc_core.h > > index f41f61aa7008..634130b589a2 100644 > > --- a/drivers/platform/x86/intel_pmc_core.h > > +++ b/drivers/platform/x86/intel_pmc_core.h > > @@ -192,8 +192,10 @@ enum ppfear_regs { > > #define ETR3_CLEAR_LPM_EVENTS_BIT 28 > > #define LPM_STS_LATCH_MODE_BIT 31 > > > > -#define TGL_NUM_IP_IGN_ALLOWED 22 > > #define TGL_PMC_SLP_S0_RES_COUNTER_STEP0x7A > > +#define TGL_PMC_LTR_THC0 0x1C04 > > +#define TGL_PMC_LTR_THC1 0x1C08 > > +#define TGL_NUM_IP_IGN_ALLOWED 23 > > #define TGL_PMC_LPM_RES_COUNTER_STEP_X261 /* 30.5us * > > 2 */ > > > > /* > > -- > > 2.25.1 > > > > > -- > Thanks, > Rajneesh -- Thanks, Rajneesh
Re: [PATCH 8/9] platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake
Acked-by: Rajneesh Bhardwaj On Wed, Mar 31, 2021 at 11:06 PM David E. Box wrote: > > From: Gayatri Kammela > > Just like Ice Lake, Tiger Lake uses Cannon Lake's LTR information > and supports a few additional registers. Hence add the LTR registers > specific to Tiger Lake to the cnp_ltr_show_map[]. > > Also adjust the number of LTR IPs for Tiger Lake to the correct amount. > > Signed-off-by: Gayatri Kammela > Signed-off-by: David E. Box > --- > drivers/platform/x86/intel_pmc_core.c | 2 ++ > drivers/platform/x86/intel_pmc_core.h | 4 +++- > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/platform/x86/intel_pmc_core.c > b/drivers/platform/x86/intel_pmc_core.c > index 458c0056e7a1..9168062c927e 100644 > --- a/drivers/platform/x86/intel_pmc_core.c > +++ b/drivers/platform/x86/intel_pmc_core.c > @@ -383,6 +383,8 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = { > * a list of core SoCs using this. > */ > {"WIGIG", ICL_PMC_LTR_WIGIG}, > + {"THC0",TGL_PMC_LTR_THC0}, > + {"THC1",TGL_PMC_LTR_THC1}, > /* Below two cannot be used for LTR_IGNORE */ > {"CURRENT_PLATFORM",CNP_PMC_LTR_CUR_PLT}, > {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, > diff --git a/drivers/platform/x86/intel_pmc_core.h > b/drivers/platform/x86/intel_pmc_core.h > index f41f61aa7008..634130b589a2 100644 > --- a/drivers/platform/x86/intel_pmc_core.h > +++ b/drivers/platform/x86/intel_pmc_core.h > @@ -192,8 +192,10 @@ enum ppfear_regs { > #define ETR3_CLEAR_LPM_EVENTS_BIT 28 > #define LPM_STS_LATCH_MODE_BIT 31 > > -#define TGL_NUM_IP_IGN_ALLOWED 22 > #define TGL_PMC_SLP_S0_RES_COUNTER_STEP0x7A > +#define TGL_PMC_LTR_THC0 0x1C04 > +#define TGL_PMC_LTR_THC1 0x1C08 > +#define TGL_NUM_IP_IGN_ALLOWED 23 > #define TGL_PMC_LPM_RES_COUNTER_STEP_X261 /* 30.5us * 2 > */ > > /* > -- > 2.25.1 > -- Thanks, Rajneesh
Re: [PATCH 8/9] platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake
Hi, On 4/1/21 5:05 AM, David E. Box wrote: > From: Gayatri Kammela > > Just like Ice Lake, Tiger Lake uses Cannon Lake's LTR information > and supports a few additional registers. Hence add the LTR registers > specific to Tiger Lake to the cnp_ltr_show_map[]. > > Also adjust the number of LTR IPs for Tiger Lake to the correct amount. > > Signed-off-by: Gayatri Kammela > Signed-off-by: David E. Box Thanks, patch looks good to me: Reviewed-by: Hans de Goede Regards, Hans > --- > drivers/platform/x86/intel_pmc_core.c | 2 ++ > drivers/platform/x86/intel_pmc_core.h | 4 +++- > 2 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/platform/x86/intel_pmc_core.c > b/drivers/platform/x86/intel_pmc_core.c > index 458c0056e7a1..9168062c927e 100644 > --- a/drivers/platform/x86/intel_pmc_core.c > +++ b/drivers/platform/x86/intel_pmc_core.c > @@ -383,6 +383,8 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = { >* a list of core SoCs using this. >*/ > {"WIGIG", ICL_PMC_LTR_WIGIG}, > + {"THC0",TGL_PMC_LTR_THC0}, > + {"THC1",TGL_PMC_LTR_THC1}, > /* Below two cannot be used for LTR_IGNORE */ > {"CURRENT_PLATFORM",CNP_PMC_LTR_CUR_PLT}, > {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, > diff --git a/drivers/platform/x86/intel_pmc_core.h > b/drivers/platform/x86/intel_pmc_core.h > index f41f61aa7008..634130b589a2 100644 > --- a/drivers/platform/x86/intel_pmc_core.h > +++ b/drivers/platform/x86/intel_pmc_core.h > @@ -192,8 +192,10 @@ enum ppfear_regs { > #define ETR3_CLEAR_LPM_EVENTS_BIT28 > #define LPM_STS_LATCH_MODE_BIT 31 > > -#define TGL_NUM_IP_IGN_ALLOWED 22 > #define TGL_PMC_SLP_S0_RES_COUNTER_STEP 0x7A > +#define TGL_PMC_LTR_THC0 0x1C04 > +#define TGL_PMC_LTR_THC1 0x1C08 > +#define TGL_NUM_IP_IGN_ALLOWED 23 > #define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */ > > /* >
[PATCH 8/9] platform/x86: intel_pmc_core: Add LTR registers for Tiger Lake
From: Gayatri Kammela Just like Ice Lake, Tiger Lake uses Cannon Lake's LTR information and supports a few additional registers. Hence add the LTR registers specific to Tiger Lake to the cnp_ltr_show_map[]. Also adjust the number of LTR IPs for Tiger Lake to the correct amount. Signed-off-by: Gayatri Kammela Signed-off-by: David E. Box --- drivers/platform/x86/intel_pmc_core.c | 2 ++ drivers/platform/x86/intel_pmc_core.h | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c index 458c0056e7a1..9168062c927e 100644 --- a/drivers/platform/x86/intel_pmc_core.c +++ b/drivers/platform/x86/intel_pmc_core.c @@ -383,6 +383,8 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = { * a list of core SoCs using this. */ {"WIGIG", ICL_PMC_LTR_WIGIG}, + {"THC0",TGL_PMC_LTR_THC0}, + {"THC1",TGL_PMC_LTR_THC1}, /* Below two cannot be used for LTR_IGNORE */ {"CURRENT_PLATFORM",CNP_PMC_LTR_CUR_PLT}, {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT}, diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h index f41f61aa7008..634130b589a2 100644 --- a/drivers/platform/x86/intel_pmc_core.h +++ b/drivers/platform/x86/intel_pmc_core.h @@ -192,8 +192,10 @@ enum ppfear_regs { #define ETR3_CLEAR_LPM_EVENTS_BIT 28 #define LPM_STS_LATCH_MODE_BIT 31 -#define TGL_NUM_IP_IGN_ALLOWED 22 #define TGL_PMC_SLP_S0_RES_COUNTER_STEP0x7A +#define TGL_PMC_LTR_THC0 0x1C04 +#define TGL_PMC_LTR_THC1 0x1C08 +#define TGL_NUM_IP_IGN_ALLOWED 23 #define TGL_PMC_LPM_RES_COUNTER_STEP_X261 /* 30.5us * 2 */ /* -- 2.25.1