[PATCH RFC v3 1/2] Devicetree: Add pl353 smc controller devicetree binding information
Add pl353 static memory controller devicetree binding information.
Signed-off-by: Punnaiah Choudary Kalluri
---
Changes in v2:
- modified timing binding info as per onfi timing parameters
- add suffix nano second as timing unit
- modified the clock names as per the IP spec
---
.../bindings/memory-controllers/pl353-smc.txt | 53
1 files changed, 53 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
new file mode 100644
index 000..c1f011d
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
@@ -0,0 +1,53 @@
+Device tree bindings for ARM PL353 static memory controller
+
+PL353 static memory controller supports two kinds of memory
+interfaces.i.e NAND and SRAM/NOR interfaces.
+The actual devices are instantiated from the child nodes of pl353 smc node.
+
+Required properties:
+- compatible : Should be "arm,pl353-smc-r2p1"
+- reg : Controller registers map and length.
+- clock-names : List of input clock names - "memclk", "aclk"
+ (See clock bindings for details).
+- clocks : Clock phandles (see clock bindings for details).
+- address-cells: Address cells, must be 1.
+- size-cells : Size cells. Must be 1.
+
+Child nodes:
+ For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are
+supported as child nodes.
+
+Mandatory timing properties for child nodes:
+- nand-tRC-ns : Read cycle time.
+- nand-tWC-ns : Write cycle time.
+- nand-tREA-ns : re_n assertion delay.
+- nand-tWP-ns : we_n de-assertion delay.
+- nand-tCLR-ns : Status read time
+- nand-tAR-ns : ID read time
+- nand-tRR-ns : busy to re_n
+
+for nand partition information please refer the below file
+Documentation/devicetree/bindings/mtd/partition.txt
+
+Example:
+ pl353smcc_0: pl353smcc@e000e000 {
+ compatible = "arm,pl353-smcc-r2p1"
+ clock-names = "memclk", "aclk";
+ clocks = < 11>, < 44>;
+ reg = <0xe000e000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ nand_0: nand@e100 {
+ compatible = "arm,pl353-nand-r2p1"
+ reg = <0xe100 0x100>;
+ nand-tRC-ns = <40>;
+ nand-tWC-ns = <40>;
+ nand-tREA-ns = <10>;
+ nand-tWP-ns = <20>;
+ nand-tCLR-ns = <20>;
+ nand-tAR-ns = <20>;
+ nand-tRR-ns = <40>;
+ (...)
+ };
+ };
--
1.7.4
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[PATCH RFC v3 1/2] Devicetree: Add pl353 smc controller devicetree binding information
Add pl353 static memory controller devicetree binding information.
Signed-off-by: Punnaiah Choudary Kalluri punn...@xilinx.com
---
Changes in v2:
- modified timing binding info as per onfi timing parameters
- add suffix nano second as timing unit
- modified the clock names as per the IP spec
---
.../bindings/memory-controllers/pl353-smc.txt | 53
1 files changed, 53 insertions(+), 0 deletions(-)
create mode 100644
Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
diff --git a/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
new file mode 100644
index 000..c1f011d
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/pl353-smc.txt
@@ -0,0 +1,53 @@
+Device tree bindings for ARM PL353 static memory controller
+
+PL353 static memory controller supports two kinds of memory
+interfaces.i.e NAND and SRAM/NOR interfaces.
+The actual devices are instantiated from the child nodes of pl353 smc node.
+
+Required properties:
+- compatible : Should be arm,pl353-smc-r2p1
+- reg : Controller registers map and length.
+- clock-names : List of input clock names - memclk, aclk
+ (See clock bindings for details).
+- clocks : Clock phandles (see clock bindings for details).
+- address-cells: Address cells, must be 1.
+- size-cells : Size cells. Must be 1.
+
+Child nodes:
+ For NAND the arm,pl353-nand-r2p1 and for NOR the cfi-flash drivers are
+supported as child nodes.
+
+Mandatory timing properties for child nodes:
+- nand-tRC-ns : Read cycle time.
+- nand-tWC-ns : Write cycle time.
+- nand-tREA-ns : re_n assertion delay.
+- nand-tWP-ns : we_n de-assertion delay.
+- nand-tCLR-ns : Status read time
+- nand-tAR-ns : ID read time
+- nand-tRR-ns : busy to re_n
+
+for nand partition information please refer the below file
+Documentation/devicetree/bindings/mtd/partition.txt
+
+Example:
+ pl353smcc_0: pl353smcc@e000e000 {
+ compatible = arm,pl353-smcc-r2p1
+ clock-names = memclk, aclk;
+ clocks = clkc 11, clkc 44;
+ reg = 0xe000e000 0x1000;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ nand_0: nand@e100 {
+ compatible = arm,pl353-nand-r2p1
+ reg = 0xe100 0x100;
+ nand-tRC-ns = 40;
+ nand-tWC-ns = 40;
+ nand-tREA-ns = 10;
+ nand-tWP-ns = 20;
+ nand-tCLR-ns = 20;
+ nand-tAR-ns = 20;
+ nand-tRR-ns = 40;
+ (...)
+ };
+ };
--
1.7.4
--
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