Re: [PATCH V2 1/2] pinctrl: tegra: add support for rcv-sel and drive type

2013-01-18 Thread Linus Walleij 
On Tue, Jan 8, 2013 at 8:32 AM, Laxman Dewangan  wrote:

> From: Pritesh Raithatha 
>
> NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e.
> rcv-sel and drive type.
>
> rcv-sel: Select between High and Normal VIL/VIH receivers.
> RCVR_SEL=1: High VIL/VIH
> RCVR_SEL=0: Normal VIL/VIH
>
> drv_type: Ouptput drive type:
> 33-50 ohm driver: 0x1
> 66-100ohm driver: 0x0
>
> Add support of these parameters to be configure from DTS file.
>
> Tegra20 and Tegra30 does not support this configuration and hence initialize 
> their
> pinmux structure with reg = -1.
>
> Originally written by Pritesh Raithatha.
> Changes by ldewangan:
> - remove drvtype_width as it is always 2.
> - Better describe the change.
>
> Signed-off-by: Pritesh Raithatha 
> Signed-off-by: Laxman Dewangan 
> Reviewed-by: Stephen Warren 

Patch applied, thanks!

Yours,
Linus Walleij
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Re: [PATCH V2 1/2] pinctrl: tegra: add support for rcv-sel and drive type

2013-01-18 Thread Linus Walleij 
On Tue, Jan 8, 2013 at 8:32 AM, Laxman Dewangan ldewan...@nvidia.com wrote:

 From: Pritesh Raithatha praitha...@nvidia.com

 NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e.
 rcv-sel and drive type.

 rcv-sel: Select between High and Normal VIL/VIH receivers.
 RCVR_SEL=1: High VIL/VIH
 RCVR_SEL=0: Normal VIL/VIH

 drv_type: Ouptput drive type:
 33-50 ohm driver: 0x1
 66-100ohm driver: 0x0

 Add support of these parameters to be configure from DTS file.

 Tegra20 and Tegra30 does not support this configuration and hence initialize 
 their
 pinmux structure with reg = -1.

 Originally written by Pritesh Raithatha.
 Changes by ldewangan:
 - remove drvtype_width as it is always 2.
 - Better describe the change.

 Signed-off-by: Pritesh Raithatha praitha...@nvidia.com
 Signed-off-by: Laxman Dewangan ldewan...@nvidia.com
 Reviewed-by: Stephen Warren swar...@nvidia.com

Patch applied, thanks!

Yours,
Linus Walleij
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Re: [PATCH V2 1/2] pinctrl: tegra: add support for rcv-sel and drive type

2013-01-15 Thread Laxman Dewangan 

Hi Linus W,


On Tuesday 08 January 2013 01:02 PM, Laxman Dewangan wrote:

From: Pritesh Raithatha 

NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e.
rcv-sel and drive type.

rcv-sel: Select between High and Normal VIL/VIH receivers.
RCVR_SEL=1: High VIL/VIH
RCVR_SEL=0: Normal VIL/VIH

drv_type: Ouptput drive type:
33-50 ohm driver: 0x1
66-100ohm driver: 0x0

Add support of these parameters to be configure from DTS file.

Tegra20 and Tegra30 does not support this configuration and hence initialize 
their
pinmux structure with reg = -1.

Originally written by Pritesh Raithatha.
Changes by ldewangan:
- remove drvtype_width as it is always 2.
- Better describe the change.

Signed-off-by: Pritesh Raithatha 
Signed-off-by: Laxman Dewangan 
Reviewed-by: Stephen Warren 
---


Can you please review the series and let us know if any thing I can do 
for closing this?


Thanks,
Laxman



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Re: [PATCH V2 1/2] pinctrl: tegra: add support for rcv-sel and drive type

2013-01-15 Thread Laxman Dewangan 

Hi Linus W,


On Tuesday 08 January 2013 01:02 PM, Laxman Dewangan wrote:

From: Pritesh Raithatha praitha...@nvidia.com

NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e.
rcv-sel and drive type.

rcv-sel: Select between High and Normal VIL/VIH receivers.
RCVR_SEL=1: High VIL/VIH
RCVR_SEL=0: Normal VIL/VIH

drv_type: Ouptput drive type:
33-50 ohm driver: 0x1
66-100ohm driver: 0x0

Add support of these parameters to be configure from DTS file.

Tegra20 and Tegra30 does not support this configuration and hence initialize 
their
pinmux structure with reg = -1.

Originally written by Pritesh Raithatha.
Changes by ldewangan:
- remove drvtype_width as it is always 2.
- Better describe the change.

Signed-off-by: Pritesh Raithatha praitha...@nvidia.com
Signed-off-by: Laxman Dewangan ldewan...@nvidia.com
Reviewed-by: Stephen Warren swar...@nvidia.com
---


Can you please review the series and let us know if any thing I can do 
for closing this?


Thanks,
Laxman



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[PATCH V2 1/2] pinctrl: tegra: add support for rcv-sel and drive type

2013-01-07 Thread Laxman Dewangan 
From: Pritesh Raithatha 

NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e.
rcv-sel and drive type.

rcv-sel: Select between High and Normal VIL/VIH receivers.
RCVR_SEL=1: High VIL/VIH
RCVR_SEL=0: Normal VIL/VIH

drv_type: Ouptput drive type:
33-50 ohm driver: 0x1
66-100ohm driver: 0x0

Add support of these parameters to be configure from DTS file.

Tegra20 and Tegra30 does not support this configuration and hence initialize 
their
pinmux structure with reg = -1.

Originally written by Pritesh Raithatha.
Changes by ldewangan:
- remove drvtype_width as it is always 2.
- Better describe the change.

Signed-off-by: Pritesh Raithatha 
Signed-off-by: Laxman Dewangan 
Reviewed-by: Stephen Warren 
---
Changes from V1:
- none in code, added Stephen in review-by.

 drivers/pinctrl/pinctrl-tegra.c   |   14 ++
 drivers/pinctrl/pinctrl-tegra.h   |   16 
 drivers/pinctrl/pinctrl-tegra20.c |6 ++
 drivers/pinctrl/pinctrl-tegra30.c |4 
 4 files changed, 40 insertions(+), 0 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index ae1e4bb..f195d77 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -201,6 +201,7 @@ static const struct cfg_param {
{"nvidia,open-drain",   TEGRA_PINCONF_PARAM_OPEN_DRAIN},
{"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
{"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
+   {"nvidia,rcv-sel",  TEGRA_PINCONF_PARAM_RCV_SEL},
{"nvidia,high-speed-mode",  TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
{"nvidia,schmitt",  TEGRA_PINCONF_PARAM_SCHMITT},
{"nvidia,low-power-mode",   TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
@@ -208,6 +209,7 @@ static const struct cfg_param {
{"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
{"nvidia,slew-rate-falling",TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
{"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
+   {"nvidia,drive-type",   TEGRA_PINCONF_PARAM_DRIVE_TYPE},
 };
 
 static int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
@@ -450,6 +452,12 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
*bit = g->ioreset_bit;
*width = 1;
break;
+   case TEGRA_PINCONF_PARAM_RCV_SEL:
+   *bank = g->rcv_sel_bank;
+   *reg = g->rcv_sel_reg;
+   *bit = g->rcv_sel_bit;
+   *width = 1;
+   break;
case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
*bank = g->drv_bank;
*reg = g->drv_reg;
@@ -492,6 +500,12 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
*bit = g->slwr_bit;
*width = g->slwr_width;
break;
+   case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
+   *bank = g->drvtype_bank;
+   *reg = g->drvtype_reg;
+   *bit = g->drvtype_bit;
+   *width = 2;
+   break;
default:
dev_err(pmx->dev, "Invalid config param %04x\n", param);
return -ENOTSUPP;
diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h
index 62e3809..817f706 100644
--- a/drivers/pinctrl/pinctrl-tegra.h
+++ b/drivers/pinctrl/pinctrl-tegra.h
@@ -30,6 +30,8 @@ enum tegra_pinconf_param {
/* argument: Boolean */
TEGRA_PINCONF_PARAM_IORESET,
/* argument: Boolean */
+   TEGRA_PINCONF_PARAM_RCV_SEL,
+   /* argument: Boolean */
TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_SCHMITT,
@@ -43,6 +45,8 @@ enum tegra_pinconf_param {
TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
/* argument: Integer, range is HW-dependant */
TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
+   /* argument: Integer, range is HW-dependant */
+   TEGRA_PINCONF_PARAM_DRIVE_TYPE,
 };
 
 enum tegra_pinconf_pull {
@@ -95,6 +99,9 @@ struct tegra_function {
  * @ioreset_reg:   IO reset register offset. -1 if unsupported.
  * @ioreset_bank:  IO reset register bank. 0 if unsupported.
  * @ioreset_bit:   IO reset register bit. 0 if unsupported.
+ * @rcv_sel_reg:   Receiver select offset. -1 if unsupported.
+ * @rcv_sel_bank:  Receiver select bank. 0 if unsupported.
+ * @rcv_sel_bit:   Receiver select bit. 0 if unsupported.
  * @drv_reg:   Drive fields register offset. -1 if unsupported.
  * This register contains the hsm, schmitt, lpmd, drvdn,
  * drvup, slwr, and slwf parameters.
@@ -110,6 +117,9 @@ struct tegra_function {
  * @slwr_width:Slew Rising field width. 0 if unsupported.
  * @slwf_bit:  Slew Falling register bit. 0 if unsupported.
  * @slwf_width:Slew Falling

[PATCH V2 1/2] pinctrl: tegra: add support for rcv-sel and drive type

2013-01-07 Thread Laxman Dewangan 
From: Pritesh Raithatha praitha...@nvidia.com

NVIDIA's Tegra114 added two more configuration parameter in pinmux i.e.
rcv-sel and drive type.

rcv-sel: Select between High and Normal VIL/VIH receivers.
RCVR_SEL=1: High VIL/VIH
RCVR_SEL=0: Normal VIL/VIH

drv_type: Ouptput drive type:
33-50 ohm driver: 0x1
66-100ohm driver: 0x0

Add support of these parameters to be configure from DTS file.

Tegra20 and Tegra30 does not support this configuration and hence initialize 
their
pinmux structure with reg = -1.

Originally written by Pritesh Raithatha.
Changes by ldewangan:
- remove drvtype_width as it is always 2.
- Better describe the change.

Signed-off-by: Pritesh Raithatha praitha...@nvidia.com
Signed-off-by: Laxman Dewangan ldewan...@nvidia.com
Reviewed-by: Stephen Warren swar...@nvidia.com
---
Changes from V1:
- none in code, added Stephen in review-by.

 drivers/pinctrl/pinctrl-tegra.c   |   14 ++
 drivers/pinctrl/pinctrl-tegra.h   |   16 
 drivers/pinctrl/pinctrl-tegra20.c |6 ++
 drivers/pinctrl/pinctrl-tegra30.c |4 
 4 files changed, 40 insertions(+), 0 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index ae1e4bb..f195d77 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -201,6 +201,7 @@ static const struct cfg_param {
{nvidia,open-drain,   TEGRA_PINCONF_PARAM_OPEN_DRAIN},
{nvidia,lock, TEGRA_PINCONF_PARAM_LOCK},
{nvidia,io-reset, TEGRA_PINCONF_PARAM_IORESET},
+   {nvidia,rcv-sel,  TEGRA_PINCONF_PARAM_RCV_SEL},
{nvidia,high-speed-mode,  TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
{nvidia,schmitt,  TEGRA_PINCONF_PARAM_SCHMITT},
{nvidia,low-power-mode,   TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
@@ -208,6 +209,7 @@ static const struct cfg_param {
{nvidia,pull-up-strength, TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
{nvidia,slew-rate-falling,TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
{nvidia,slew-rate-rising, TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
+   {nvidia,drive-type,   TEGRA_PINCONF_PARAM_DRIVE_TYPE},
 };
 
 static int tegra_pinctrl_dt_subnode_to_map(struct device *dev,
@@ -450,6 +452,12 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
*bit = g-ioreset_bit;
*width = 1;
break;
+   case TEGRA_PINCONF_PARAM_RCV_SEL:
+   *bank = g-rcv_sel_bank;
+   *reg = g-rcv_sel_reg;
+   *bit = g-rcv_sel_bit;
+   *width = 1;
+   break;
case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
*bank = g-drv_bank;
*reg = g-drv_reg;
@@ -492,6 +500,12 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
*bit = g-slwr_bit;
*width = g-slwr_width;
break;
+   case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
+   *bank = g-drvtype_bank;
+   *reg = g-drvtype_reg;
+   *bit = g-drvtype_bit;
+   *width = 2;
+   break;
default:
dev_err(pmx-dev, Invalid config param %04x\n, param);
return -ENOTSUPP;
diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h
index 62e3809..817f706 100644
--- a/drivers/pinctrl/pinctrl-tegra.h
+++ b/drivers/pinctrl/pinctrl-tegra.h
@@ -30,6 +30,8 @@ enum tegra_pinconf_param {
/* argument: Boolean */
TEGRA_PINCONF_PARAM_IORESET,
/* argument: Boolean */
+   TEGRA_PINCONF_PARAM_RCV_SEL,
+   /* argument: Boolean */
TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE,
/* argument: Boolean */
TEGRA_PINCONF_PARAM_SCHMITT,
@@ -43,6 +45,8 @@ enum tegra_pinconf_param {
TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING,
/* argument: Integer, range is HW-dependant */
TEGRA_PINCONF_PARAM_SLEW_RATE_RISING,
+   /* argument: Integer, range is HW-dependant */
+   TEGRA_PINCONF_PARAM_DRIVE_TYPE,
 };
 
 enum tegra_pinconf_pull {
@@ -95,6 +99,9 @@ struct tegra_function {
  * @ioreset_reg:   IO reset register offset. -1 if unsupported.
  * @ioreset_bank:  IO reset register bank. 0 if unsupported.
  * @ioreset_bit:   IO reset register bit. 0 if unsupported.
+ * @rcv_sel_reg:   Receiver select offset. -1 if unsupported.
+ * @rcv_sel_bank:  Receiver select bank. 0 if unsupported.
+ * @rcv_sel_bit:   Receiver select bit. 0 if unsupported.
  * @drv_reg:   Drive fields register offset. -1 if unsupported.
  * This register contains the hsm, schmitt, lpmd, drvdn,
  * drvup, slwr, and slwf parameters.
@@ -110,6 +117,9 @@ struct tegra_function {
  * @slwr_width:Slew Rising field width. 0 if unsupported.
  * @slwf_bit:  Slew Falling register bit. 0 if unsupported.