Re: [PATCH V2 10/11] coresight: sink: Add TRBE driver
On 1/15/21 6:13 PM, Suzuki K Poulose wrote:
> On 1/15/21 5:29 AM, Anshuman Khandual wrote:
>>
>>
>> On 1/13/21 8:58 PM, Suzuki K Poulose wrote:
>>> Hi Anshuman,
>>>
>>> The driver looks overall good to me. Please find some minor comments below
Sure.
>>>
>>> On 1/13/21 4:18 AM, Anshuman Khandual wrote:
Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
accessible via the system registers. The TRBE supports different addressing
modes including CPU virtual address and buffer modes including the circular
buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
access to the trace buffer could be prohibited by a higher exception level
(EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
private interrupt (PPI) on address translation errors and when the buffer
is full. Overall implementation here is inspired from the Arm SPE driver.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Signed-off-by: Anshuman Khandual
>
> ...
>
+
+/*
+ * TRBE Buffer Management
+ *
+ * The TRBE buffer spans from the base pointer till the limit pointer.
When enabled,
+ * it starts writing trace data from the write pointer onward till the
limit pointer.
>>>
>>>
+ * When the write pointer reaches the address just before the limit
pointer, it gets
+ * wrapped around again to the base pointer. This is called a TRBE wrap
event, which
+ * generates a maintenance interrupt when operated in WRAP or STOP mode.
>>>
>>> According to the TRM, it is FILL mode, instead of STOP. So please change
>>> the above to:
>>>
>>> "operated in WRAP or FILL mode".
Changed.
>>
>> Updated.
>>
>>>
>>>
The write
+ * pointer again starts writing trace data from the base pointer until
just before
+ * the limit pointer before getting wrapped again with an IRQ and this
process just
+ * goes on as long as the TRBE is enabled.
>>>
>>> This could be dropped as it applies to WRAP/CIRCULAR buffer mode, which we
>>> don't use.
>>
>> Probably this could be changed a bit to match the FILL mode. Because it is
>> essential
>> to describe the continuous nature of the buffer operation, even in the FILL
>> mode.
>>
>> * After TRBE
>> * IRQ gets handled and enabled again, write pointer again starts writing
>> trace data
>> * from the base pointer until just before the limit pointer before getting
>> wrapped
>> * again with an IRQ and this process just goes on as long as the TRBE is
>> enabled.
>>
>
> The above doesn't parse well and kind of repeats the operation of TRBE which
> is
> already explained above. How about :
>
+ * When the write pointer reaches the address just before the limit
pointer, it gets
+ * wrapped around again to the base pointer. This is called a TRBE wrap
event, which
+ * generates a maintenance interrupt when operated in WRAP or STOP mode.
>
> This driver uses FILL mode, where the TRBE stops the trace collection at wrap
> event.
> The IRQ handler updates the AUX buffer and re-enables the TRBE with updated
> WRITE and
> LIMIT pointers.
Updated.
>
>
+
+static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
+ struct perf_event *event, void **pages,
+ int nr_pages, bool snapshot)
+{
+ struct trbe_buf *buf;
+ struct page **pglist;
+ int i;
+
+ if ((nr_pages < 2) || (snapshot && (nr_pages & 1)))
>>>
>>> This restriction on snapshot could be removed now, since we use the
>>> full buffer.
>>
>> Dropped only the second condition here i.e (snapshot && (nr_pages & 1).
>> Just wondering if the aux buffer could work with a single page so that
>> the first condition can also be dropped.
>
> I think it is good to keep the restriction of 2 pages, as the WRITE_PTR
> and the LIMIT_PTR must be page aligned. With a single page, you can't do
> much, with writing into a partially filled buffer. This may be added
> as a comment to explain the restriction.
Added the above comment.
>
+
+static enum trbe_fault_action trbe_get_fault_act(struct
perf_output_handle *handle)
+{
+ int ec = get_trbe_ec();
+ int bsc = get_trbe_bsc();
+
+ WARN_ON(is_trbe_running());
+ if (is_trbe_trg() || is_trbe_abort())
>>>
>>> We seem to be reading the TRBSR every single in these helpers. Could we
>>> optimise them
>>> by passing the register value in ?
>>
>> The same goes for get_trbe_ec() and get_trbe_bsc() as well. Probably all
>> TRBSR field probing helpers should be modified to accept a TRBSR register
>> value instead.
>>
>>>
>>> i.e
>>> u64 trbsr = get_trbe_status();
>>>
>>> WARN_ON(is_trbe_runnign(trbsr))
>>> if (is_trbe_trg(trbsr) ||
Re: [PATCH V2 10/11] coresight: sink: Add TRBE driver
On 1/15/21 5:29 AM, Anshuman Khandual wrote:
On 1/13/21 8:58 PM, Suzuki K Poulose wrote:
Hi Anshuman,
The driver looks overall good to me. Please find some minor comments below
On 1/13/21 4:18 AM, Anshuman Khandual wrote:
Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is
accessible via the system registers. The TRBE supports different addressing
modes including CPU virtual address and buffer modes including the circular
buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1),
an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the
access to the trace buffer could be prohibited by a higher exception level
(EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU
private interrupt (PPI) on address translation errors and when the buffer
is full. Overall implementation here is inspired from the Arm SPE driver.
Cc: Mathieu Poirier
Cc: Mike Leach
Cc: Suzuki K Poulose
Signed-off-by: Anshuman Khandual
...
+
+/*
+ * TRBE Buffer Management
+ *
+ * The TRBE buffer spans from the base pointer till the limit pointer. When
enabled,
+ * it starts writing trace data from the write pointer onward till the limit
pointer.
+ * When the write pointer reaches the address just before the limit pointer,
it gets
+ * wrapped around again to the base pointer. This is called a TRBE wrap event,
which
+ * generates a maintenance interrupt when operated in WRAP or STOP mode.
According to the TRM, it is FILL mode, instead of STOP. So please change the
above to:
"operated in WRAP or FILL mode".
Updated.
The write
+ * pointer again starts writing trace data from the base pointer until just
before
+ * the limit pointer before getting wrapped again with an IRQ and this process
just
+ * goes on as long as the TRBE is enabled.
This could be dropped as it applies to WRAP/CIRCULAR buffer mode, which we
don't use.
Probably this could be changed a bit to match the FILL mode. Because it is
essential
to describe the continuous nature of the buffer operation, even in the FILL
mode.
* After TRBE
* IRQ gets handled and enabled again, write pointer again starts writing
trace data
* from the base pointer until just before the limit pointer before getting
wrapped
* again with an IRQ and this process just goes on as long as the TRBE is
enabled.
The above doesn't parse well and kind of repeats the operation of TRBE which is
already explained above. How about :
>>> + * When the write pointer reaches the address just before the limit
pointer, it gets
>>> + * wrapped around again to the base pointer. This is called a TRBE wrap
event, which
>>> + * generates a maintenance interrupt when operated in WRAP or STOP mode.
This driver uses FILL mode, where the TRBE stops the trace collection at wrap
event.
The IRQ handler updates the AUX buffer and re-enables the TRBE with updated
WRITE and
LIMIT pointers.
+
+static void *arm_trbe_alloc_buffer(struct coresight_device *csdev,
+ struct perf_event *event, void **pages,
+ int nr_pages, bool snapshot)
+{
+ struct trbe_buf *buf;
+ struct page **pglist;
+ int i;
+
+ if ((nr_pages < 2) || (snapshot && (nr_pages & 1)))
This restriction on snapshot could be removed now, since we use the
full buffer.
Dropped only the second condition here i.e (snapshot && (nr_pages & 1).
Just wondering if the aux buffer could work with a single page so that
the first condition can also be dropped.
I think it is good to keep the restriction of 2 pages, as the WRITE_PTR
and the LIMIT_PTR must be page aligned. With a single page, you can't do
much, with writing into a partially filled buffer. This may be added
as a comment to explain the restriction.
+
+static enum trbe_fault_action trbe_get_fault_act(struct perf_output_handle
*handle)
+{
+ int ec = get_trbe_ec();
+ int bsc = get_trbe_bsc();
+
+ WARN_ON(is_trbe_running());
+ if (is_trbe_trg() || is_trbe_abort())
We seem to be reading the TRBSR every single in these helpers. Could we
optimise them
by passing the register value in ?
The same goes for get_trbe_ec() and get_trbe_bsc() as well. Probably all
TRBSR field probing helpers should be modified to accept a TRBSR register
value instead.
i.e
u64 trbsr = get_trbe_status();
WARN_ON(is_trbe_runnign(trbsr))
if (is_trbe_trg(trbsr) || is_trbe_abort(trbsr))
For is_trbe_wrap() too
Yes.
We should skip the driver init, if the kernel is unmapped at EL0,
as the TRBE can't safely write to the kernel virtual addressed
buffer when the CPU is running at EL0. This is unlikely, but we
should cover that case.
This should be sufficient or it needs a pr_err() as well ?
Please add a pr_err() message to indicate why this failed. Otherwise
the user could be left with no clue.
Cheers
Suzuki
Re: [PATCH V2 10/11] coresight: sink: Add TRBE driver
On 1/13/21 8:58 PM, Suzuki K Poulose wrote: > Hi Anshuman, > > The driver looks overall good to me. Please find some minor comments below > > On 1/13/21 4:18 AM, Anshuman Khandual wrote: >> Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is >> accessible via the system registers. The TRBE supports different addressing >> modes including CPU virtual address and buffer modes including the circular >> buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1), >> an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the >> access to the trace buffer could be prohibited by a higher exception level >> (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU >> private interrupt (PPI) on address translation errors and when the buffer >> is full. Overall implementation here is inspired from the Arm SPE driver. >> >> Cc: Mathieu Poirier >> Cc: Mike Leach >> Cc: Suzuki K Poulose >> Signed-off-by: Anshuman Khandual >> --- >> Changes in V2: >> >> - Dropped irq from coresight sysfs documentation >> - Renamed get_trbe_limit() as compute_trbe_buffer_limit() >> - Dropped SYSTEM_RUNNING check for system_state >> - Dropped .data value from arm_trbe_of_match[] >> - Dropped [set|get]_trbe_[trig|fill]_mode() helpers >> - Dropped clearing TRBSR_FSC_MASK from TRBE status register >> - Added a comment in arm_trbe_update_buffer() >> - Updated comment for ETE_IGNORE_PACKET >> - Updated comment for basic TRBE operation >> - Updated TRBE buffer and trigger mode macros >> - Restructured trbe_enable_hw() >> - Updated trbe_snapshot_offset() to use the entire buffer >> - Changed dsb(ish) as dsb(nsh) during the buffer flush >> - Renamed set_trbe_flush() as trbe_drain_buffer() >> - Renamed trbe_disable_and_drain_local() as trbe_drain_and_disable_local() >> - Reworked sync in trbe_enable_hw(), trbe_update_buffer() and >> arm_trbe_irq_handler() >> >> Documentation/trace/coresight/coresight-trbe.rst | 39 + >> arch/arm64/include/asm/sysreg.h | 2 + >> drivers/hwtracing/coresight/Kconfig | 11 + >> drivers/hwtracing/coresight/Makefile | 1 + >> drivers/hwtracing/coresight/coresight-trbe.c | 966 >> +++ >> drivers/hwtracing/coresight/coresight-trbe.h | 216 + >> 6 files changed, 1235 insertions(+) >> create mode 100644 Documentation/trace/coresight/coresight-trbe.rst >> create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c >> create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h >> >> diff --git a/Documentation/trace/coresight/coresight-trbe.rst >> b/Documentation/trace/coresight/coresight-trbe.rst >> new file mode 100644 >> index 000..1cbb819 >> --- /dev/null >> +++ b/Documentation/trace/coresight/coresight-trbe.rst >> @@ -0,0 +1,39 @@ >> +.. SPDX-License-Identifier: GPL-2.0 >> + >> +== >> +Trace Buffer Extension (TRBE). >> +== >> + >> + :Author: Anshuman Khandual >> + :Date: November 2020 >> + >> +Hardware Description >> + >> + >> +Trace Buffer Extension (TRBE) is a percpu hardware which captures in system >> +memory, CPU traces generated from a corresponding percpu tracing unit. This >> +gets plugged in as a coresight sink device because the corresponding trace >> +genarators (ETE), are plugged in as source device. >> + >> +The TRBE is not compliant to CoreSight architecture specifications, but is >> +driven via the CoreSight driver framework to support the ETE (which is >> +CoreSight compliant) integration. >> + >> +Sysfs files and directories >> +--- >> + >> +The TRBE devices appear on the existing coresight bus alongside the other >> +coresight devices:: >> + >> + >$ ls /sys/bus/coresight/devices >> + trbe0 trbe1 trbe2 trbe3 >> + >> +The ``trbe`` named TRBEs are associated with a CPU.:: >> + >> + >$ ls /sys/bus/coresight/devices/trbe0/ >> + align dbm >> + >> +*Key file items are:-* >> + * ``align``: TRBE write pointer alignment >> + * ``dbm``: TRBE updates memory with access and dirty flags >> + >> diff --git a/arch/arm64/include/asm/sysreg.h >> b/arch/arm64/include/asm/sysreg.h >> index d60750e7..d7e65f0 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -97,6 +97,7 @@ >> #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | >> ((!!x) << PSTATE_Imm_shift)) >> #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | >> ((!!x) << PSTATE_Imm_shift)) >> #define SET_PSTATE_TCO(x) __emit_inst(0xd500401f | PSTATE_TCO | >> ((!!x) << PSTATE_Imm_shift)) >> +#define TSB_CSYNC __emit_inst(0xd503225f) >> #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) >> #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) >> @@ -880,6 +881,7 @@ >> #define ID_AA64MMFR2_CNP_SHIFT 0 >>
Re: [PATCH V2 10/11] coresight: sink: Add TRBE driver
Hi Anshuman, The driver looks overall good to me. Please find some minor comments below On 1/13/21 4:18 AM, Anshuman Khandual wrote: Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is accessible via the system registers. The TRBE supports different addressing modes including CPU virtual address and buffer modes including the circular buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1), an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the access to the trace buffer could be prohibited by a higher exception level (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU private interrupt (PPI) on address translation errors and when the buffer is full. Overall implementation here is inspired from the Arm SPE driver. Cc: Mathieu Poirier Cc: Mike Leach Cc: Suzuki K Poulose Signed-off-by: Anshuman Khandual --- Changes in V2: - Dropped irq from coresight sysfs documentation - Renamed get_trbe_limit() as compute_trbe_buffer_limit() - Dropped SYSTEM_RUNNING check for system_state - Dropped .data value from arm_trbe_of_match[] - Dropped [set|get]_trbe_[trig|fill]_mode() helpers - Dropped clearing TRBSR_FSC_MASK from TRBE status register - Added a comment in arm_trbe_update_buffer() - Updated comment for ETE_IGNORE_PACKET - Updated comment for basic TRBE operation - Updated TRBE buffer and trigger mode macros - Restructured trbe_enable_hw() - Updated trbe_snapshot_offset() to use the entire buffer - Changed dsb(ish) as dsb(nsh) during the buffer flush - Renamed set_trbe_flush() as trbe_drain_buffer() - Renamed trbe_disable_and_drain_local() as trbe_drain_and_disable_local() - Reworked sync in trbe_enable_hw(), trbe_update_buffer() and arm_trbe_irq_handler() Documentation/trace/coresight/coresight-trbe.rst | 39 + arch/arm64/include/asm/sysreg.h | 2 + drivers/hwtracing/coresight/Kconfig | 11 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-trbe.c | 966 +++ drivers/hwtracing/coresight/coresight-trbe.h | 216 + 6 files changed, 1235 insertions(+) create mode 100644 Documentation/trace/coresight/coresight-trbe.rst create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h diff --git a/Documentation/trace/coresight/coresight-trbe.rst b/Documentation/trace/coresight/coresight-trbe.rst new file mode 100644 index 000..1cbb819 --- /dev/null +++ b/Documentation/trace/coresight/coresight-trbe.rst @@ -0,0 +1,39 @@ +.. SPDX-License-Identifier: GPL-2.0 + +== +Trace Buffer Extension (TRBE). +== + +:Author: Anshuman Khandual +:Date: November 2020 + +Hardware Description + + +Trace Buffer Extension (TRBE) is a percpu hardware which captures in system +memory, CPU traces generated from a corresponding percpu tracing unit. This +gets plugged in as a coresight sink device because the corresponding trace +genarators (ETE), are plugged in as source device. + +The TRBE is not compliant to CoreSight architecture specifications, but is +driven via the CoreSight driver framework to support the ETE (which is +CoreSight compliant) integration. + +Sysfs files and directories +--- + +The TRBE devices appear on the existing coresight bus alongside the other +coresight devices:: + + >$ ls /sys/bus/coresight/devices + trbe0 trbe1 trbe2 trbe3 + +The ``trbe`` named TRBEs are associated with a CPU.:: + + >$ ls /sys/bus/coresight/devices/trbe0/ +align dbm + +*Key file items are:-* + * ``align``: TRBE write pointer alignment + * ``dbm``: TRBE updates memory with access and dirty flags + diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index d60750e7..d7e65f0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -97,6 +97,7 @@ #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) #define SET_PSTATE_SSBS(x)__emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) #define SET_PSTATE_TCO(x) __emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift)) +#define TSB_CSYNC __emit_inst(0xd503225f) #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) @@ -880,6 +881,7 @@ #define ID_AA64MMFR2_CNP_SHIFT0 /* id_aa64dfr0 */ +#define ID_AA64DFR0_TRBE_SHIFT 44 #define ID_AA64DFR0_TRACE_FILT_SHIFT 40 #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 #define ID_AA64DFR0_PMSVER_SHIFT 32 diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index f154ae7..aa657ab 100644 ---
[PATCH V2 10/11] coresight: sink: Add TRBE driver
Trace Buffer Extension (TRBE) implements a trace buffer per CPU which is accessible via the system registers. The TRBE supports different addressing modes including CPU virtual address and buffer modes including the circular buffer mode. The TRBE buffer is addressed by a base pointer (TRBBASER_EL1), an write pointer (TRBPTR_EL1) and a limit pointer (TRBLIMITR_EL1). But the access to the trace buffer could be prohibited by a higher exception level (EL3 or EL2), indicated by TRBIDR_EL1.P. The TRBE can also generate a CPU private interrupt (PPI) on address translation errors and when the buffer is full. Overall implementation here is inspired from the Arm SPE driver. Cc: Mathieu Poirier Cc: Mike Leach Cc: Suzuki K Poulose Signed-off-by: Anshuman Khandual --- Changes in V2: - Dropped irq from coresight sysfs documentation - Renamed get_trbe_limit() as compute_trbe_buffer_limit() - Dropped SYSTEM_RUNNING check for system_state - Dropped .data value from arm_trbe_of_match[] - Dropped [set|get]_trbe_[trig|fill]_mode() helpers - Dropped clearing TRBSR_FSC_MASK from TRBE status register - Added a comment in arm_trbe_update_buffer() - Updated comment for ETE_IGNORE_PACKET - Updated comment for basic TRBE operation - Updated TRBE buffer and trigger mode macros - Restructured trbe_enable_hw() - Updated trbe_snapshot_offset() to use the entire buffer - Changed dsb(ish) as dsb(nsh) during the buffer flush - Renamed set_trbe_flush() as trbe_drain_buffer() - Renamed trbe_disable_and_drain_local() as trbe_drain_and_disable_local() - Reworked sync in trbe_enable_hw(), trbe_update_buffer() and arm_trbe_irq_handler() Documentation/trace/coresight/coresight-trbe.rst | 39 + arch/arm64/include/asm/sysreg.h | 2 + drivers/hwtracing/coresight/Kconfig | 11 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-trbe.c | 966 +++ drivers/hwtracing/coresight/coresight-trbe.h | 216 + 6 files changed, 1235 insertions(+) create mode 100644 Documentation/trace/coresight/coresight-trbe.rst create mode 100644 drivers/hwtracing/coresight/coresight-trbe.c create mode 100644 drivers/hwtracing/coresight/coresight-trbe.h diff --git a/Documentation/trace/coresight/coresight-trbe.rst b/Documentation/trace/coresight/coresight-trbe.rst new file mode 100644 index 000..1cbb819 --- /dev/null +++ b/Documentation/trace/coresight/coresight-trbe.rst @@ -0,0 +1,39 @@ +.. SPDX-License-Identifier: GPL-2.0 + +== +Trace Buffer Extension (TRBE). +== + +:Author: Anshuman Khandual +:Date: November 2020 + +Hardware Description + + +Trace Buffer Extension (TRBE) is a percpu hardware which captures in system +memory, CPU traces generated from a corresponding percpu tracing unit. This +gets plugged in as a coresight sink device because the corresponding trace +genarators (ETE), are plugged in as source device. + +The TRBE is not compliant to CoreSight architecture specifications, but is +driven via the CoreSight driver framework to support the ETE (which is +CoreSight compliant) integration. + +Sysfs files and directories +--- + +The TRBE devices appear on the existing coresight bus alongside the other +coresight devices:: + + >$ ls /sys/bus/coresight/devices + trbe0 trbe1 trbe2 trbe3 + +The ``trbe`` named TRBEs are associated with a CPU.:: + + >$ ls /sys/bus/coresight/devices/trbe0/ +align dbm + +*Key file items are:-* + * ``align``: TRBE write pointer alignment + * ``dbm``: TRBE updates memory with access and dirty flags + diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index d60750e7..d7e65f0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -97,6 +97,7 @@ #define SET_PSTATE_UAO(x) __emit_inst(0xd500401f | PSTATE_UAO | ((!!x) << PSTATE_Imm_shift)) #define SET_PSTATE_SSBS(x) __emit_inst(0xd500401f | PSTATE_SSBS | ((!!x) << PSTATE_Imm_shift)) #define SET_PSTATE_TCO(x) __emit_inst(0xd500401f | PSTATE_TCO | ((!!x) << PSTATE_Imm_shift)) +#define TSB_CSYNC __emit_inst(0xd503225f) #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) @@ -880,6 +881,7 @@ #define ID_AA64MMFR2_CNP_SHIFT 0 /* id_aa64dfr0 */ +#define ID_AA64DFR0_TRBE_SHIFT 44 #define ID_AA64DFR0_TRACE_FILT_SHIFT 40 #define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 #define ID_AA64DFR0_PMSVER_SHIFT 32 diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig index f154ae7..aa657ab 100644 --- a/drivers/hwtracing/coresight/Kconfig +++ b/drivers/hwtracing/coresight/Kconfig @@ -164,6 +164,17 @@ config CORESIGHT_CTI To compile this driver as a module, choose M
