Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Jaehoon Chung]

Hi,

On 01/16/2017 05:37 PM, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Wednesday 04 January 2017 06:04 PM, Jaehoon Chung wrote:
>> This patch supports to use Generic Phy framework for Exynos PCIe phy.
>> When Exynos that supported the pcie want to use the PCIe,
>> it needs to control the phy resgister.
>> But it should be more complex to control in their own PCIe device drivers.
>>
>> Currently, there is an exynos5440 case to support the pcie.
>> So this driver is based on Exynos5440 PCIe.
>> In future, will support the Other exynos SoCs likes exynos5433, exynos7.
> 
> please re-write the commit message.

Will update the commit-message

>>
>> Signed-off-by: Jaehoon Chung 
>> ---
>> Changelog on V2:
>> - Not include the codes relevant to pci-exynos.
>> - Remove the getting child node.
>>
>>  drivers/phy/Kconfig   |   9 ++
>>  drivers/phy/Makefile  |   1 +
>>  drivers/phy/phy-exynos-pcie.c | 280 
>> ++
>>  3 files changed, 290 insertions(+)
>>  create mode 100644 drivers/phy/phy-exynos-pcie.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index e8eb7f2..2dddef4 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
>>This driver provides PHY interface for USB 3.0 DRD controller
>>present on Exynos5 SoC series.
>>  
>> +config PHY_EXYNOS_PCIE
>> +bool "Exynos PCIe PHY driver"
>> +depends on ARCH_EXYNOS && OF
> 
> include COMPILE_TEST

Ok.

>> +depends on PCI_EXYNOS
> 
> PCI_EXYNOS should depend on PHY_EXYNOS_PCIE if at all required. Or else do 
> away
> with this dependency.

Ok.

>> +select GENERIC_PHY
>> +help
>> +  Enable PCIe PHY support for Exynos SoC series.
>> +  This driver provides PHY interface for Exynos PCIe controller.
>> +
>>  config PHY_PISTACHIO_USB
>>  tristate "IMG Pistachio USB2.0 PHY driver"
>>  depends on MACH_PISTACHIO
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index 65eb2f4..081aeb4 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)  += 
>> phy-exynos4x12-usb2.o
>>  phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)   += phy-exynos5250-usb2.o
>>  phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)  += phy-s5pv210-usb2.o
>>  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)+= phy-exynos5-usbdrd.o
>> +obj-$(CONFIG_PHY_EXYNOS_PCIE)   += phy-exynos-pcie.o
>>  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
>>  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)+= phy-rockchip-inno-usb2.o
>> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
>> new file mode 100644
>> index 000..b57f49b
>> --- /dev/null
>> +++ b/drivers/phy/phy-exynos-pcie.c
>> @@ -0,0 +1,280 @@
>> +/*
>> + * Samsung EXYNOS SoC series PCIe PHY driver
>> + *
>> + * Phy provider for PCIe controller on Exynos SoC series
>> + *
>> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.
> 
> 2017?

When i had posted the first version, it was 2016.. :)

>> + * Jaehoon Chung 
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +/* PCIe Purple registers */
>> +#define PCIE_PHY_GLOBAL_RESET   0x000
>> +#define PCIE_PHY_COMMON_RESET   0x004
>> +#define PCIE_PHY_CMN_REG0x008
>> +#define PCIE_PHY_MAC_RESET  0x00c
>> +#define PCIE_PHY_PLL_LOCKED 0x010
>> +#define PCIE_PHY_TRSVREG_RESET  0x020
>> +#define PCIE_PHY_TRSV_RESET 0x024
> 
> Please use BIT() macro for bit definitions.

Ok.

>> +
>> +/* PCIe PHY registers */
>> +#define PCIE_PHY_IMPEDANCE  0x004
>> +#define PCIE_PHY_PLL_DIV_0  0x008
>> +#define PCIE_PHY_PLL_BIAS   0x00c
>> +#define PCIE_PHY_DCC_FEEDBACK   0x014
>> +#define PCIE_PHY_PLL_DIV_1  0x05c
>> +#define PCIE_PHY_COMMON_POWER   0x064
>> +#define PCIE_PHY_COMMON_PD_CMN  BIT(3)
>> +#define PCIE_PHY_TRSV0_EMP_LVL  0x084
>> +#define PCIE_PHY_TRSV0_DRV_LVL  0x088
>> +#define PCIE_PHY_TRSV0_RXCDR0x0ac
>> +#define PCIE_PHY_TRSV0_POWER0x0c4
>> +#define PCIE_PHY_TRSV0_PD_TSV   BIT(7)
>> +#define PCIE_PHY_TRSV0_LVCC 0x0dc
>> +#define PCIE_PHY_TRSV1_EMP_LVL  0x144
>> +#define PCIE_PHY_TRSV1_RXCDR0x16c
>> +#define PCIE_PHY_TRSV1_POWER0x184
>> +#define PCIE_PHY_TRSV1_PD_TSV   BIT(7)
>> +#define PCIE_PHY_TRSV1_LVCC 0x19c
>> +#define 

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Jaehoon Chung]

Hi,

On 01/16/2017 05:37 PM, Kishon Vijay Abraham I wrote:
> Hi,
> 
> On Wednesday 04 January 2017 06:04 PM, Jaehoon Chung wrote:
>> This patch supports to use Generic Phy framework for Exynos PCIe phy.
>> When Exynos that supported the pcie want to use the PCIe,
>> it needs to control the phy resgister.
>> But it should be more complex to control in their own PCIe device drivers.
>>
>> Currently, there is an exynos5440 case to support the pcie.
>> So this driver is based on Exynos5440 PCIe.
>> In future, will support the Other exynos SoCs likes exynos5433, exynos7.
> 
> please re-write the commit message.

Will update the commit-message

>>
>> Signed-off-by: Jaehoon Chung 
>> ---
>> Changelog on V2:
>> - Not include the codes relevant to pci-exynos.
>> - Remove the getting child node.
>>
>>  drivers/phy/Kconfig   |   9 ++
>>  drivers/phy/Makefile  |   1 +
>>  drivers/phy/phy-exynos-pcie.c | 280 
>> ++
>>  3 files changed, 290 insertions(+)
>>  create mode 100644 drivers/phy/phy-exynos-pcie.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index e8eb7f2..2dddef4 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
>>This driver provides PHY interface for USB 3.0 DRD controller
>>present on Exynos5 SoC series.
>>  
>> +config PHY_EXYNOS_PCIE
>> +bool "Exynos PCIe PHY driver"
>> +depends on ARCH_EXYNOS && OF
> 
> include COMPILE_TEST

Ok.

>> +depends on PCI_EXYNOS
> 
> PCI_EXYNOS should depend on PHY_EXYNOS_PCIE if at all required. Or else do 
> away
> with this dependency.

Ok.

>> +select GENERIC_PHY
>> +help
>> +  Enable PCIe PHY support for Exynos SoC series.
>> +  This driver provides PHY interface for Exynos PCIe controller.
>> +
>>  config PHY_PISTACHIO_USB
>>  tristate "IMG Pistachio USB2.0 PHY driver"
>>  depends on MACH_PISTACHIO
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index 65eb2f4..081aeb4 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)  += 
>> phy-exynos4x12-usb2.o
>>  phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)   += phy-exynos5250-usb2.o
>>  phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)  += phy-s5pv210-usb2.o
>>  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)+= phy-exynos5-usbdrd.o
>> +obj-$(CONFIG_PHY_EXYNOS_PCIE)   += phy-exynos-pcie.o
>>  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
>>  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)+= phy-rockchip-inno-usb2.o
>> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
>> new file mode 100644
>> index 000..b57f49b
>> --- /dev/null
>> +++ b/drivers/phy/phy-exynos-pcie.c
>> @@ -0,0 +1,280 @@
>> +/*
>> + * Samsung EXYNOS SoC series PCIe PHY driver
>> + *
>> + * Phy provider for PCIe controller on Exynos SoC series
>> + *
>> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.
> 
> 2017?

When i had posted the first version, it was 2016.. :)

>> + * Jaehoon Chung 
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +/* PCIe Purple registers */
>> +#define PCIE_PHY_GLOBAL_RESET   0x000
>> +#define PCIE_PHY_COMMON_RESET   0x004
>> +#define PCIE_PHY_CMN_REG0x008
>> +#define PCIE_PHY_MAC_RESET  0x00c
>> +#define PCIE_PHY_PLL_LOCKED 0x010
>> +#define PCIE_PHY_TRSVREG_RESET  0x020
>> +#define PCIE_PHY_TRSV_RESET 0x024
> 
> Please use BIT() macro for bit definitions.

Ok.

>> +
>> +/* PCIe PHY registers */
>> +#define PCIE_PHY_IMPEDANCE  0x004
>> +#define PCIE_PHY_PLL_DIV_0  0x008
>> +#define PCIE_PHY_PLL_BIAS   0x00c
>> +#define PCIE_PHY_DCC_FEEDBACK   0x014
>> +#define PCIE_PHY_PLL_DIV_1  0x05c
>> +#define PCIE_PHY_COMMON_POWER   0x064
>> +#define PCIE_PHY_COMMON_PD_CMN  BIT(3)
>> +#define PCIE_PHY_TRSV0_EMP_LVL  0x084
>> +#define PCIE_PHY_TRSV0_DRV_LVL  0x088
>> +#define PCIE_PHY_TRSV0_RXCDR0x0ac
>> +#define PCIE_PHY_TRSV0_POWER0x0c4
>> +#define PCIE_PHY_TRSV0_PD_TSV   BIT(7)
>> +#define PCIE_PHY_TRSV0_LVCC 0x0dc
>> +#define PCIE_PHY_TRSV1_EMP_LVL  0x144
>> +#define PCIE_PHY_TRSV1_RXCDR0x16c
>> +#define PCIE_PHY_TRSV1_POWER0x184
>> +#define PCIE_PHY_TRSV1_PD_TSV   BIT(7)
>> +#define PCIE_PHY_TRSV1_LVCC 0x19c
>> +#define PCIE_PHY_TRSV2_EMP_LVL  0x204
>> +#define 

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Kishon Vijay Abraham I]

Hi,

On Wednesday 04 January 2017 06:04 PM, Jaehoon Chung wrote:
> This patch supports to use Generic Phy framework for Exynos PCIe phy.
> When Exynos that supported the pcie want to use the PCIe,
> it needs to control the phy resgister.
> But it should be more complex to control in their own PCIe device drivers.
> 
> Currently, there is an exynos5440 case to support the pcie.
> So this driver is based on Exynos5440 PCIe.
> In future, will support the Other exynos SoCs likes exynos5433, exynos7.

please re-write the commit message.
> 
> Signed-off-by: Jaehoon Chung 
> ---
> Changelog on V2:
> - Not include the codes relevant to pci-exynos.
> - Remove the getting child node.
> 
>  drivers/phy/Kconfig   |   9 ++
>  drivers/phy/Makefile  |   1 +
>  drivers/phy/phy-exynos-pcie.c | 280 
> ++
>  3 files changed, 290 insertions(+)
>  create mode 100644 drivers/phy/phy-exynos-pcie.c
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index e8eb7f2..2dddef4 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
> This driver provides PHY interface for USB 3.0 DRD controller
> present on Exynos5 SoC series.
>  
> +config PHY_EXYNOS_PCIE
> + bool "Exynos PCIe PHY driver"
> + depends on ARCH_EXYNOS && OF

include COMPILE_TEST
> + depends on PCI_EXYNOS

PCI_EXYNOS should depend on PHY_EXYNOS_PCIE if at all required. Or else do away
with this dependency.
> + select GENERIC_PHY
> + help
> +   Enable PCIe PHY support for Exynos SoC series.
> +   This driver provides PHY interface for Exynos PCIe controller.
> +
>  config PHY_PISTACHIO_USB
>   tristate "IMG Pistachio USB2.0 PHY driver"
>   depends on MACH_PISTACHIO
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 65eb2f4..081aeb4 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)   += 
> phy-exynos4x12-usb2.o
>  phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)+= phy-exynos5250-usb2.o
>  phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)   += phy-s5pv210-usb2.o
>  obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
> +obj-$(CONFIG_PHY_EXYNOS_PCIE)+= phy-exynos-pcie.o
>  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)  += phy-qcom-apq8064-sata.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
> new file mode 100644
> index 000..b57f49b
> --- /dev/null
> +++ b/drivers/phy/phy-exynos-pcie.c
> @@ -0,0 +1,280 @@
> +/*
> + * Samsung EXYNOS SoC series PCIe PHY driver
> + *
> + * Phy provider for PCIe controller on Exynos SoC series
> + *
> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.

2017?
> + * Jaehoon Chung 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* PCIe Purple registers */
> +#define PCIE_PHY_GLOBAL_RESET0x000
> +#define PCIE_PHY_COMMON_RESET0x004
> +#define PCIE_PHY_CMN_REG 0x008
> +#define PCIE_PHY_MAC_RESET   0x00c
> +#define PCIE_PHY_PLL_LOCKED  0x010
> +#define PCIE_PHY_TRSVREG_RESET   0x020
> +#define PCIE_PHY_TRSV_RESET  0x024

Please use BIT() macro for bit definitions.
> +
> +/* PCIe PHY registers */
> +#define PCIE_PHY_IMPEDANCE   0x004
> +#define PCIE_PHY_PLL_DIV_0   0x008
> +#define PCIE_PHY_PLL_BIAS0x00c
> +#define PCIE_PHY_DCC_FEEDBACK0x014
> +#define PCIE_PHY_PLL_DIV_1   0x05c
> +#define PCIE_PHY_COMMON_POWER0x064
> +#define PCIE_PHY_COMMON_PD_CMN   BIT(3)
> +#define PCIE_PHY_TRSV0_EMP_LVL   0x084
> +#define PCIE_PHY_TRSV0_DRV_LVL   0x088
> +#define PCIE_PHY_TRSV0_RXCDR 0x0ac
> +#define PCIE_PHY_TRSV0_POWER 0x0c4
> +#define PCIE_PHY_TRSV0_PD_TSVBIT(7)
> +#define PCIE_PHY_TRSV0_LVCC  0x0dc
> +#define PCIE_PHY_TRSV1_EMP_LVL   0x144
> +#define PCIE_PHY_TRSV1_RXCDR 0x16c
> +#define PCIE_PHY_TRSV1_POWER 0x184
> +#define PCIE_PHY_TRSV1_PD_TSVBIT(7)
> +#define PCIE_PHY_TRSV1_LVCC  0x19c
> +#define PCIE_PHY_TRSV2_EMP_LVL   0x204
> +#define PCIE_PHY_TRSV2_RXCDR 0x22c
> +#define PCIE_PHY_TRSV2_POWER 0x244
> +#define PCIE_PHY_TRSV2_PD_TSVBIT(7)
> +#define PCIE_PHY_TRSV2_LVCC  0x25c
> +#define PCIE_PHY_TRSV3_EMP_LVL   0x2c4
> +#define 

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Kishon Vijay Abraham I]

Hi,

On Wednesday 04 January 2017 06:04 PM, Jaehoon Chung wrote:
> This patch supports to use Generic Phy framework for Exynos PCIe phy.
> When Exynos that supported the pcie want to use the PCIe,
> it needs to control the phy resgister.
> But it should be more complex to control in their own PCIe device drivers.
> 
> Currently, there is an exynos5440 case to support the pcie.
> So this driver is based on Exynos5440 PCIe.
> In future, will support the Other exynos SoCs likes exynos5433, exynos7.

please re-write the commit message.
> 
> Signed-off-by: Jaehoon Chung 
> ---
> Changelog on V2:
> - Not include the codes relevant to pci-exynos.
> - Remove the getting child node.
> 
>  drivers/phy/Kconfig   |   9 ++
>  drivers/phy/Makefile  |   1 +
>  drivers/phy/phy-exynos-pcie.c | 280 
> ++
>  3 files changed, 290 insertions(+)
>  create mode 100644 drivers/phy/phy-exynos-pcie.c
> 
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index e8eb7f2..2dddef4 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
> This driver provides PHY interface for USB 3.0 DRD controller
> present on Exynos5 SoC series.
>  
> +config PHY_EXYNOS_PCIE
> + bool "Exynos PCIe PHY driver"
> + depends on ARCH_EXYNOS && OF

include COMPILE_TEST
> + depends on PCI_EXYNOS

PCI_EXYNOS should depend on PHY_EXYNOS_PCIE if at all required. Or else do away
with this dependency.
> + select GENERIC_PHY
> + help
> +   Enable PCIe PHY support for Exynos SoC series.
> +   This driver provides PHY interface for Exynos PCIe controller.
> +
>  config PHY_PISTACHIO_USB
>   tristate "IMG Pistachio USB2.0 PHY driver"
>   depends on MACH_PISTACHIO
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 65eb2f4..081aeb4 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)   += 
> phy-exynos4x12-usb2.o
>  phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)+= phy-exynos5250-usb2.o
>  phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)   += phy-s5pv210-usb2.o
>  obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
> +obj-$(CONFIG_PHY_EXYNOS_PCIE)+= phy-exynos-pcie.o
>  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)  += phy-qcom-apq8064-sata.o
>  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>  obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
> new file mode 100644
> index 000..b57f49b
> --- /dev/null
> +++ b/drivers/phy/phy-exynos-pcie.c
> @@ -0,0 +1,280 @@
> +/*
> + * Samsung EXYNOS SoC series PCIe PHY driver
> + *
> + * Phy provider for PCIe controller on Exynos SoC series
> + *
> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.

2017?
> + * Jaehoon Chung 
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* PCIe Purple registers */
> +#define PCIE_PHY_GLOBAL_RESET0x000
> +#define PCIE_PHY_COMMON_RESET0x004
> +#define PCIE_PHY_CMN_REG 0x008
> +#define PCIE_PHY_MAC_RESET   0x00c
> +#define PCIE_PHY_PLL_LOCKED  0x010
> +#define PCIE_PHY_TRSVREG_RESET   0x020
> +#define PCIE_PHY_TRSV_RESET  0x024

Please use BIT() macro for bit definitions.
> +
> +/* PCIe PHY registers */
> +#define PCIE_PHY_IMPEDANCE   0x004
> +#define PCIE_PHY_PLL_DIV_0   0x008
> +#define PCIE_PHY_PLL_BIAS0x00c
> +#define PCIE_PHY_DCC_FEEDBACK0x014
> +#define PCIE_PHY_PLL_DIV_1   0x05c
> +#define PCIE_PHY_COMMON_POWER0x064
> +#define PCIE_PHY_COMMON_PD_CMN   BIT(3)
> +#define PCIE_PHY_TRSV0_EMP_LVL   0x084
> +#define PCIE_PHY_TRSV0_DRV_LVL   0x088
> +#define PCIE_PHY_TRSV0_RXCDR 0x0ac
> +#define PCIE_PHY_TRSV0_POWER 0x0c4
> +#define PCIE_PHY_TRSV0_PD_TSVBIT(7)
> +#define PCIE_PHY_TRSV0_LVCC  0x0dc
> +#define PCIE_PHY_TRSV1_EMP_LVL   0x144
> +#define PCIE_PHY_TRSV1_RXCDR 0x16c
> +#define PCIE_PHY_TRSV1_POWER 0x184
> +#define PCIE_PHY_TRSV1_PD_TSVBIT(7)
> +#define PCIE_PHY_TRSV1_LVCC  0x19c
> +#define PCIE_PHY_TRSV2_EMP_LVL   0x204
> +#define PCIE_PHY_TRSV2_RXCDR 0x22c
> +#define PCIE_PHY_TRSV2_POWER 0x244
> +#define PCIE_PHY_TRSV2_PD_TSVBIT(7)
> +#define PCIE_PHY_TRSV2_LVCC  0x25c
> +#define PCIE_PHY_TRSV3_EMP_LVL   0x2c4
> +#define PCIE_PHY_TRSV3_RXCDR 0x2ec
> +#define 

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Jaehoon Chung]

Hi Vivek,

On 01/10/2017 03:07 PM, Vivek Gautam wrote:
> Hi Jaehoon,
> 
> 
> On 01/04/2017 06:04 PM, Jaehoon Chung wrote:
>> This patch supports to use Generic Phy framework for Exynos PCIe phy.
>> When Exynos that supported the pcie want to use the PCIe,
>> it needs to control the phy resgister.
>> But it should be more complex to control in their own PCIe device drivers.
>>
>> Currently, there is an exynos5440 case to support the pcie.
>> So this driver is based on Exynos5440 PCIe.
>> In future, will support the Other exynos SoCs likes exynos5433, exynos7.
>>
>> Signed-off-by: Jaehoon Chung 
>> ---
>> Changelog on V2:
>> - Not include the codes relevant to pci-exynos.
>> - Remove the getting child node.
>>
>>   drivers/phy/Kconfig   |   9 ++
>>   drivers/phy/Makefile  |   1 +
>>   drivers/phy/phy-exynos-pcie.c | 280 
>> ++
>>   3 files changed, 290 insertions(+)
>>   create mode 100644 drivers/phy/phy-exynos-pcie.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index e8eb7f2..2dddef4 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
>> This driver provides PHY interface for USB 3.0 DRD controller
>> present on Exynos5 SoC series.
>>   +config PHY_EXYNOS_PCIE
>> +bool "Exynos PCIe PHY driver"
>> +depends on ARCH_EXYNOS && OF
>> +depends on PCI_EXYNOS
>> +select GENERIC_PHY
>> +help
>> +  Enable PCIe PHY support for Exynos SoC series.
>> +  This driver provides PHY interface for Exynos PCIe controller.
>> +
>>   config PHY_PISTACHIO_USB
>>   tristate "IMG Pistachio USB2.0 PHY driver"
>>   depends on MACH_PISTACHIO
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index 65eb2f4..081aeb4 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)+= 
>> phy-exynos4x12-usb2.o
>>   phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)+= phy-exynos5250-usb2.o
>>   phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)+= phy-s5pv210-usb2.o
>>   obj-$(CONFIG_PHY_EXYNOS5_USBDRD)+= phy-exynos5-usbdrd.o
>> +obj-$(CONFIG_PHY_EXYNOS_PCIE)+= phy-exynos-pcie.o
>>   obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
>>   obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>>   obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)+= phy-rockchip-inno-usb2.o
>> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
>> new file mode 100644
>> index 000..b57f49b
>> --- /dev/null
>> +++ b/drivers/phy/phy-exynos-pcie.c
>> @@ -0,0 +1,280 @@
>> +/*
>> + * Samsung EXYNOS SoC series PCIe PHY driver
>> + *
>> + * Phy provider for PCIe controller on Exynos SoC series
>> + *
>> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.
>> + * Jaehoon Chung 
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +/* PCIe Purple registers */
>> +#define PCIE_PHY_GLOBAL_RESET0x000
>> +#define PCIE_PHY_COMMON_RESET0x004
>> +#define PCIE_PHY_CMN_REG0x008
>> +#define PCIE_PHY_MAC_RESET0x00c
>> +#define PCIE_PHY_PLL_LOCKED0x010
>> +#define PCIE_PHY_TRSVREG_RESET0x020
>> +#define PCIE_PHY_TRSV_RESET0x024
>> +
>> +/* PCIe PHY registers */
>> +#define PCIE_PHY_IMPEDANCE0x004
>> +#define PCIE_PHY_PLL_DIV_00x008
>> +#define PCIE_PHY_PLL_BIAS0x00c
>> +#define PCIE_PHY_DCC_FEEDBACK0x014
>> +#define PCIE_PHY_PLL_DIV_10x05c
>> +#define PCIE_PHY_COMMON_POWER0x064
>> +#define PCIE_PHY_COMMON_PD_CMNBIT(3)
>> +#define PCIE_PHY_TRSV0_EMP_LVL0x084
>> +#define PCIE_PHY_TRSV0_DRV_LVL0x088
>> +#define PCIE_PHY_TRSV0_RXCDR0x0ac
>> +#define PCIE_PHY_TRSV0_POWER0x0c4
>> +#define PCIE_PHY_TRSV0_PD_TSVBIT(7)
>> +#define PCIE_PHY_TRSV0_LVCC0x0dc
>> +#define PCIE_PHY_TRSV1_EMP_LVL0x144
>> +#define PCIE_PHY_TRSV1_RXCDR0x16c
>> +#define PCIE_PHY_TRSV1_POWER0x184
>> +#define PCIE_PHY_TRSV1_PD_TSVBIT(7)
>> +#define PCIE_PHY_TRSV1_LVCC0x19c
>> +#define PCIE_PHY_TRSV2_EMP_LVL0x204
>> +#define PCIE_PHY_TRSV2_RXCDR0x22c
>> +#define PCIE_PHY_TRSV2_POWER0x244
>> +#define PCIE_PHY_TRSV2_PD_TSVBIT(7)
>> +#define PCIE_PHY_TRSV2_LVCC0x25c
>> +#define PCIE_PHY_TRSV3_EMP_LVL0x2c4
>> +#define PCIE_PHY_TRSV3_RXCDR0x2ec
>> +#define PCIE_PHY_TRSV3_POWER0x304
>> +#define PCIE_PHY_TRSV3_PD_TSVBIT(7)
>> +#define PCIE_PHY_TRSV3_LVCC0x31c
>> +
>> +struct 

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Jaehoon Chung]

Hi Vivek,

On 01/10/2017 03:07 PM, Vivek Gautam wrote:
> Hi Jaehoon,
> 
> 
> On 01/04/2017 06:04 PM, Jaehoon Chung wrote:
>> This patch supports to use Generic Phy framework for Exynos PCIe phy.
>> When Exynos that supported the pcie want to use the PCIe,
>> it needs to control the phy resgister.
>> But it should be more complex to control in their own PCIe device drivers.
>>
>> Currently, there is an exynos5440 case to support the pcie.
>> So this driver is based on Exynos5440 PCIe.
>> In future, will support the Other exynos SoCs likes exynos5433, exynos7.
>>
>> Signed-off-by: Jaehoon Chung 
>> ---
>> Changelog on V2:
>> - Not include the codes relevant to pci-exynos.
>> - Remove the getting child node.
>>
>>   drivers/phy/Kconfig   |   9 ++
>>   drivers/phy/Makefile  |   1 +
>>   drivers/phy/phy-exynos-pcie.c | 280 
>> ++
>>   3 files changed, 290 insertions(+)
>>   create mode 100644 drivers/phy/phy-exynos-pcie.c
>>
>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>> index e8eb7f2..2dddef4 100644
>> --- a/drivers/phy/Kconfig
>> +++ b/drivers/phy/Kconfig
>> @@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
>> This driver provides PHY interface for USB 3.0 DRD controller
>> present on Exynos5 SoC series.
>>   +config PHY_EXYNOS_PCIE
>> +bool "Exynos PCIe PHY driver"
>> +depends on ARCH_EXYNOS && OF
>> +depends on PCI_EXYNOS
>> +select GENERIC_PHY
>> +help
>> +  Enable PCIe PHY support for Exynos SoC series.
>> +  This driver provides PHY interface for Exynos PCIe controller.
>> +
>>   config PHY_PISTACHIO_USB
>>   tristate "IMG Pistachio USB2.0 PHY driver"
>>   depends on MACH_PISTACHIO
>> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
>> index 65eb2f4..081aeb4 100644
>> --- a/drivers/phy/Makefile
>> +++ b/drivers/phy/Makefile
>> @@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2)+= 
>> phy-exynos4x12-usb2.o
>>   phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)+= phy-exynos5250-usb2.o
>>   phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)+= phy-s5pv210-usb2.o
>>   obj-$(CONFIG_PHY_EXYNOS5_USBDRD)+= phy-exynos5-usbdrd.o
>> +obj-$(CONFIG_PHY_EXYNOS_PCIE)+= phy-exynos-pcie.o
>>   obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
>>   obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
>>   obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)+= phy-rockchip-inno-usb2.o
>> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
>> new file mode 100644
>> index 000..b57f49b
>> --- /dev/null
>> +++ b/drivers/phy/phy-exynos-pcie.c
>> @@ -0,0 +1,280 @@
>> +/*
>> + * Samsung EXYNOS SoC series PCIe PHY driver
>> + *
>> + * Phy provider for PCIe controller on Exynos SoC series
>> + *
>> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.
>> + * Jaehoon Chung 
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +/* PCIe Purple registers */
>> +#define PCIE_PHY_GLOBAL_RESET0x000
>> +#define PCIE_PHY_COMMON_RESET0x004
>> +#define PCIE_PHY_CMN_REG0x008
>> +#define PCIE_PHY_MAC_RESET0x00c
>> +#define PCIE_PHY_PLL_LOCKED0x010
>> +#define PCIE_PHY_TRSVREG_RESET0x020
>> +#define PCIE_PHY_TRSV_RESET0x024
>> +
>> +/* PCIe PHY registers */
>> +#define PCIE_PHY_IMPEDANCE0x004
>> +#define PCIE_PHY_PLL_DIV_00x008
>> +#define PCIE_PHY_PLL_BIAS0x00c
>> +#define PCIE_PHY_DCC_FEEDBACK0x014
>> +#define PCIE_PHY_PLL_DIV_10x05c
>> +#define PCIE_PHY_COMMON_POWER0x064
>> +#define PCIE_PHY_COMMON_PD_CMNBIT(3)
>> +#define PCIE_PHY_TRSV0_EMP_LVL0x084
>> +#define PCIE_PHY_TRSV0_DRV_LVL0x088
>> +#define PCIE_PHY_TRSV0_RXCDR0x0ac
>> +#define PCIE_PHY_TRSV0_POWER0x0c4
>> +#define PCIE_PHY_TRSV0_PD_TSVBIT(7)
>> +#define PCIE_PHY_TRSV0_LVCC0x0dc
>> +#define PCIE_PHY_TRSV1_EMP_LVL0x144
>> +#define PCIE_PHY_TRSV1_RXCDR0x16c
>> +#define PCIE_PHY_TRSV1_POWER0x184
>> +#define PCIE_PHY_TRSV1_PD_TSVBIT(7)
>> +#define PCIE_PHY_TRSV1_LVCC0x19c
>> +#define PCIE_PHY_TRSV2_EMP_LVL0x204
>> +#define PCIE_PHY_TRSV2_RXCDR0x22c
>> +#define PCIE_PHY_TRSV2_POWER0x244
>> +#define PCIE_PHY_TRSV2_PD_TSVBIT(7)
>> +#define PCIE_PHY_TRSV2_LVCC0x25c
>> +#define PCIE_PHY_TRSV3_EMP_LVL0x2c4
>> +#define PCIE_PHY_TRSV3_RXCDR0x2ec
>> +#define PCIE_PHY_TRSV3_POWER0x304
>> +#define PCIE_PHY_TRSV3_PD_TSVBIT(7)
>> +#define PCIE_PHY_TRSV3_LVCC0x31c
>> +
>> +struct exynos_pcie_phy_data {
>> +struct phy_ops*ops;
>> +};

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Vivek Gautam]

Hi Jaehoon,


On 01/04/2017 06:04 PM, Jaehoon Chung wrote:

This patch supports to use Generic Phy framework for Exynos PCIe phy.
When Exynos that supported the pcie want to use the PCIe,
it needs to control the phy resgister.
But it should be more complex to control in their own PCIe device drivers.

Currently, there is an exynos5440 case to support the pcie.
So this driver is based on Exynos5440 PCIe.
In future, will support the Other exynos SoCs likes exynos5433, exynos7.

Signed-off-by: Jaehoon Chung 
---
Changelog on V2:
- Not include the codes relevant to pci-exynos.
- Remove the getting child node.

  drivers/phy/Kconfig   |   9 ++
  drivers/phy/Makefile  |   1 +
  drivers/phy/phy-exynos-pcie.c | 280 ++
  3 files changed, 290 insertions(+)
  create mode 100644 drivers/phy/phy-exynos-pcie.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e8eb7f2..2dddef4 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
  This driver provides PHY interface for USB 3.0 DRD controller
  present on Exynos5 SoC series.
  
+config PHY_EXYNOS_PCIE

+   bool "Exynos PCIe PHY driver"
+   depends on ARCH_EXYNOS && OF
+   depends on PCI_EXYNOS
+   select GENERIC_PHY
+   help
+ Enable PCIe PHY support for Exynos SoC series.
+ This driver provides PHY interface for Exynos PCIe controller.
+
  config PHY_PISTACHIO_USB
tristate "IMG Pistachio USB2.0 PHY driver"
depends on MACH_PISTACHIO
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 65eb2f4..081aeb4 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += 
phy-exynos4x12-usb2.o
  phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
  phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)+= phy-s5pv210-usb2.o
  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)  += phy-exynos5-usbdrd.o
+obj-$(CONFIG_PHY_EXYNOS_PCIE)  += phy-exynos-pcie.o
  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)   += phy-qcom-apq8064-sata.o
  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
  obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)  += phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
new file mode 100644
index 000..b57f49b
--- /dev/null
+++ b/drivers/phy/phy-exynos-pcie.c
@@ -0,0 +1,280 @@
+/*
+ * Samsung EXYNOS SoC series PCIe PHY driver
+ *
+ * Phy provider for PCIe controller on Exynos SoC series
+ *
+ * Copyright (C) 2016 Samsung Electronics Co., Ltd.
+ * Jaehoon Chung 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PCIe Purple registers */
+#define PCIE_PHY_GLOBAL_RESET  0x000
+#define PCIE_PHY_COMMON_RESET  0x004
+#define PCIE_PHY_CMN_REG   0x008
+#define PCIE_PHY_MAC_RESET 0x00c
+#define PCIE_PHY_PLL_LOCKED0x010
+#define PCIE_PHY_TRSVREG_RESET 0x020
+#define PCIE_PHY_TRSV_RESET0x024
+
+/* PCIe PHY registers */
+#define PCIE_PHY_IMPEDANCE 0x004
+#define PCIE_PHY_PLL_DIV_0 0x008
+#define PCIE_PHY_PLL_BIAS  0x00c
+#define PCIE_PHY_DCC_FEEDBACK  0x014
+#define PCIE_PHY_PLL_DIV_1 0x05c
+#define PCIE_PHY_COMMON_POWER  0x064
+#define PCIE_PHY_COMMON_PD_CMN BIT(3)
+#define PCIE_PHY_TRSV0_EMP_LVL 0x084
+#define PCIE_PHY_TRSV0_DRV_LVL 0x088
+#define PCIE_PHY_TRSV0_RXCDR   0x0ac
+#define PCIE_PHY_TRSV0_POWER   0x0c4
+#define PCIE_PHY_TRSV0_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV0_LVCC0x0dc
+#define PCIE_PHY_TRSV1_EMP_LVL 0x144
+#define PCIE_PHY_TRSV1_RXCDR   0x16c
+#define PCIE_PHY_TRSV1_POWER   0x184
+#define PCIE_PHY_TRSV1_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV1_LVCC0x19c
+#define PCIE_PHY_TRSV2_EMP_LVL 0x204
+#define PCIE_PHY_TRSV2_RXCDR   0x22c
+#define PCIE_PHY_TRSV2_POWER   0x244
+#define PCIE_PHY_TRSV2_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV2_LVCC0x25c
+#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
+#define PCIE_PHY_TRSV3_RXCDR   0x2ec
+#define PCIE_PHY_TRSV3_POWER   0x304
+#define PCIE_PHY_TRSV3_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV3_LVCC0x31c
+
+struct exynos_pcie_phy_data {
+   struct phy_ops  *ops;
+};
+
+/* For Exynos pcie phy */
+struct exynos_pcie_phy {
+   const struct exynos_pcie_phy_data *drv_data;
+   void __iomem *phy_base;
+   void __iomem *blk_base; /* For exynos5440 */
+};
+
+static void exynos_pcie_phy_writel(void __iomem *base, u32 

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Vivek Gautam]

Hi Jaehoon,


On 01/04/2017 06:04 PM, Jaehoon Chung wrote:

This patch supports to use Generic Phy framework for Exynos PCIe phy.
When Exynos that supported the pcie want to use the PCIe,
it needs to control the phy resgister.
But it should be more complex to control in their own PCIe device drivers.

Currently, there is an exynos5440 case to support the pcie.
So this driver is based on Exynos5440 PCIe.
In future, will support the Other exynos SoCs likes exynos5433, exynos7.

Signed-off-by: Jaehoon Chung 
---
Changelog on V2:
- Not include the codes relevant to pci-exynos.
- Remove the getting child node.

  drivers/phy/Kconfig   |   9 ++
  drivers/phy/Makefile  |   1 +
  drivers/phy/phy-exynos-pcie.c | 280 ++
  3 files changed, 290 insertions(+)
  create mode 100644 drivers/phy/phy-exynos-pcie.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e8eb7f2..2dddef4 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
  This driver provides PHY interface for USB 3.0 DRD controller
  present on Exynos5 SoC series.
  
+config PHY_EXYNOS_PCIE

+   bool "Exynos PCIe PHY driver"
+   depends on ARCH_EXYNOS && OF
+   depends on PCI_EXYNOS
+   select GENERIC_PHY
+   help
+ Enable PCIe PHY support for Exynos SoC series.
+ This driver provides PHY interface for Exynos PCIe controller.
+
  config PHY_PISTACHIO_USB
tristate "IMG Pistachio USB2.0 PHY driver"
depends on MACH_PISTACHIO
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 65eb2f4..081aeb4 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += 
phy-exynos4x12-usb2.o
  phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
  phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2)+= phy-s5pv210-usb2.o
  obj-$(CONFIG_PHY_EXYNOS5_USBDRD)  += phy-exynos5-usbdrd.o
+obj-$(CONFIG_PHY_EXYNOS_PCIE)  += phy-exynos-pcie.o
  obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)   += phy-qcom-apq8064-sata.o
  obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
  obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)  += phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
new file mode 100644
index 000..b57f49b
--- /dev/null
+++ b/drivers/phy/phy-exynos-pcie.c
@@ -0,0 +1,280 @@
+/*
+ * Samsung EXYNOS SoC series PCIe PHY driver
+ *
+ * Phy provider for PCIe controller on Exynos SoC series
+ *
+ * Copyright (C) 2016 Samsung Electronics Co., Ltd.
+ * Jaehoon Chung 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PCIe Purple registers */
+#define PCIE_PHY_GLOBAL_RESET  0x000
+#define PCIE_PHY_COMMON_RESET  0x004
+#define PCIE_PHY_CMN_REG   0x008
+#define PCIE_PHY_MAC_RESET 0x00c
+#define PCIE_PHY_PLL_LOCKED0x010
+#define PCIE_PHY_TRSVREG_RESET 0x020
+#define PCIE_PHY_TRSV_RESET0x024
+
+/* PCIe PHY registers */
+#define PCIE_PHY_IMPEDANCE 0x004
+#define PCIE_PHY_PLL_DIV_0 0x008
+#define PCIE_PHY_PLL_BIAS  0x00c
+#define PCIE_PHY_DCC_FEEDBACK  0x014
+#define PCIE_PHY_PLL_DIV_1 0x05c
+#define PCIE_PHY_COMMON_POWER  0x064
+#define PCIE_PHY_COMMON_PD_CMN BIT(3)
+#define PCIE_PHY_TRSV0_EMP_LVL 0x084
+#define PCIE_PHY_TRSV0_DRV_LVL 0x088
+#define PCIE_PHY_TRSV0_RXCDR   0x0ac
+#define PCIE_PHY_TRSV0_POWER   0x0c4
+#define PCIE_PHY_TRSV0_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV0_LVCC0x0dc
+#define PCIE_PHY_TRSV1_EMP_LVL 0x144
+#define PCIE_PHY_TRSV1_RXCDR   0x16c
+#define PCIE_PHY_TRSV1_POWER   0x184
+#define PCIE_PHY_TRSV1_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV1_LVCC0x19c
+#define PCIE_PHY_TRSV2_EMP_LVL 0x204
+#define PCIE_PHY_TRSV2_RXCDR   0x22c
+#define PCIE_PHY_TRSV2_POWER   0x244
+#define PCIE_PHY_TRSV2_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV2_LVCC0x25c
+#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
+#define PCIE_PHY_TRSV3_RXCDR   0x2ec
+#define PCIE_PHY_TRSV3_POWER   0x304
+#define PCIE_PHY_TRSV3_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV3_LVCC0x31c
+
+struct exynos_pcie_phy_data {
+   struct phy_ops  *ops;
+};
+
+/* For Exynos pcie phy */
+struct exynos_pcie_phy {
+   const struct exynos_pcie_phy_data *drv_data;
+   void __iomem *phy_base;
+   void __iomem *blk_base; /* For exynos5440 */
+};
+
+static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
+{
+   writel(val, base + 

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Alim Akhtar]

Hi,

On 01/04/2017 06:04 PM, Jaehoon Chung wrote:

This patch supports to use Generic Phy framework for Exynos PCIe phy.
When Exynos that supported the pcie want to use the PCIe,
it needs to control the phy resgister.
But it should be more complex to control in their own PCIe device drivers.

Currently, there is an exynos5440 case to support the pcie.
So this driver is based on Exynos5440 PCIe.
In future, will support the Other exynos SoCs likes exynos5433, exynos7.

Signed-off-by: Jaehoon Chung 
---
Changelog on V2:
- Not include the codes relevant to pci-exynos.
- Remove the getting child node.

 drivers/phy/Kconfig   |   9 ++
 drivers/phy/Makefile  |   1 +
 drivers/phy/phy-exynos-pcie.c | 280 ++
 3 files changed, 290 insertions(+)
 create mode 100644 drivers/phy/phy-exynos-pcie.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e8eb7f2..2dddef4 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
  This driver provides PHY interface for USB 3.0 DRD controller
  present on Exynos5 SoC series.

+config PHY_EXYNOS_PCIE
+   bool "Exynos PCIe PHY driver"
+   depends on ARCH_EXYNOS && OF


Please add a depends on COMPILE_TEST as well.
Apart from this looks ok.



+   depends on PCI_EXYNOS
+   select GENERIC_PHY
+   help
+ Enable PCIe PHY support for Exynos SoC series.
+ This driver provides PHY interface for Exynos PCIe controller.
+
 config PHY_PISTACHIO_USB
tristate "IMG Pistachio USB2.0 PHY driver"
depends on MACH_PISTACHIO
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 65eb2f4..081aeb4 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += 
phy-exynos4x12-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)  += phy-exynos5250-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)   += phy-exynos5-usbdrd.o
+obj-$(CONFIG_PHY_EXYNOS_PCIE)  += phy-exynos-pcie.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)   += phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
new file mode 100644
index 000..b57f49b
--- /dev/null
+++ b/drivers/phy/phy-exynos-pcie.c
@@ -0,0 +1,280 @@
+/*
+ * Samsung EXYNOS SoC series PCIe PHY driver
+ *
+ * Phy provider for PCIe controller on Exynos SoC series
+ *
+ * Copyright (C) 2016 Samsung Electronics Co., Ltd.
+ * Jaehoon Chung 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PCIe Purple registers */
+#define PCIE_PHY_GLOBAL_RESET  0x000
+#define PCIE_PHY_COMMON_RESET  0x004
+#define PCIE_PHY_CMN_REG   0x008
+#define PCIE_PHY_MAC_RESET 0x00c
+#define PCIE_PHY_PLL_LOCKED0x010
+#define PCIE_PHY_TRSVREG_RESET 0x020
+#define PCIE_PHY_TRSV_RESET0x024
+
+/* PCIe PHY registers */
+#define PCIE_PHY_IMPEDANCE 0x004
+#define PCIE_PHY_PLL_DIV_0 0x008
+#define PCIE_PHY_PLL_BIAS  0x00c
+#define PCIE_PHY_DCC_FEEDBACK  0x014
+#define PCIE_PHY_PLL_DIV_1 0x05c
+#define PCIE_PHY_COMMON_POWER  0x064
+#define PCIE_PHY_COMMON_PD_CMN BIT(3)
+#define PCIE_PHY_TRSV0_EMP_LVL 0x084
+#define PCIE_PHY_TRSV0_DRV_LVL 0x088
+#define PCIE_PHY_TRSV0_RXCDR   0x0ac
+#define PCIE_PHY_TRSV0_POWER   0x0c4
+#define PCIE_PHY_TRSV0_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV0_LVCC0x0dc
+#define PCIE_PHY_TRSV1_EMP_LVL 0x144
+#define PCIE_PHY_TRSV1_RXCDR   0x16c
+#define PCIE_PHY_TRSV1_POWER   0x184
+#define PCIE_PHY_TRSV1_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV1_LVCC0x19c
+#define PCIE_PHY_TRSV2_EMP_LVL 0x204
+#define PCIE_PHY_TRSV2_RXCDR   0x22c
+#define PCIE_PHY_TRSV2_POWER   0x244
+#define PCIE_PHY_TRSV2_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV2_LVCC0x25c
+#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
+#define PCIE_PHY_TRSV3_RXCDR   0x2ec
+#define PCIE_PHY_TRSV3_POWER   0x304
+#define PCIE_PHY_TRSV3_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV3_LVCC0x31c
+
+struct exynos_pcie_phy_data {
+   struct phy_ops  *ops;
+};
+
+/* For Exynos pcie phy */
+struct exynos_pcie_phy {
+   const struct exynos_pcie_phy_data *drv_data;
+   void __iomem *phy_base;
+   void __iomem *blk_base; /* For exynos5440 */
+};
+

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Alim Akhtar]

Hi,

On 01/04/2017 06:04 PM, Jaehoon Chung wrote:

This patch supports to use Generic Phy framework for Exynos PCIe phy.
When Exynos that supported the pcie want to use the PCIe,
it needs to control the phy resgister.
But it should be more complex to control in their own PCIe device drivers.

Currently, there is an exynos5440 case to support the pcie.
So this driver is based on Exynos5440 PCIe.
In future, will support the Other exynos SoCs likes exynos5433, exynos7.

Signed-off-by: Jaehoon Chung 
---
Changelog on V2:
- Not include the codes relevant to pci-exynos.
- Remove the getting child node.

 drivers/phy/Kconfig   |   9 ++
 drivers/phy/Makefile  |   1 +
 drivers/phy/phy-exynos-pcie.c | 280 ++
 3 files changed, 290 insertions(+)
 create mode 100644 drivers/phy/phy-exynos-pcie.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e8eb7f2..2dddef4 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
  This driver provides PHY interface for USB 3.0 DRD controller
  present on Exynos5 SoC series.

+config PHY_EXYNOS_PCIE
+   bool "Exynos PCIe PHY driver"
+   depends on ARCH_EXYNOS && OF


Please add a depends on COMPILE_TEST as well.
Apart from this looks ok.



+   depends on PCI_EXYNOS
+   select GENERIC_PHY
+   help
+ Enable PCIe PHY support for Exynos SoC series.
+ This driver provides PHY interface for Exynos PCIe controller.
+
 config PHY_PISTACHIO_USB
tristate "IMG Pistachio USB2.0 PHY driver"
depends on MACH_PISTACHIO
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 65eb2f4..081aeb4 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += 
phy-exynos4x12-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)  += phy-exynos5250-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)   += phy-exynos5-usbdrd.o
+obj-$(CONFIG_PHY_EXYNOS_PCIE)  += phy-exynos-pcie.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)   += phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
new file mode 100644
index 000..b57f49b
--- /dev/null
+++ b/drivers/phy/phy-exynos-pcie.c
@@ -0,0 +1,280 @@
+/*
+ * Samsung EXYNOS SoC series PCIe PHY driver
+ *
+ * Phy provider for PCIe controller on Exynos SoC series
+ *
+ * Copyright (C) 2016 Samsung Electronics Co., Ltd.
+ * Jaehoon Chung 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PCIe Purple registers */
+#define PCIE_PHY_GLOBAL_RESET  0x000
+#define PCIE_PHY_COMMON_RESET  0x004
+#define PCIE_PHY_CMN_REG   0x008
+#define PCIE_PHY_MAC_RESET 0x00c
+#define PCIE_PHY_PLL_LOCKED0x010
+#define PCIE_PHY_TRSVREG_RESET 0x020
+#define PCIE_PHY_TRSV_RESET0x024
+
+/* PCIe PHY registers */
+#define PCIE_PHY_IMPEDANCE 0x004
+#define PCIE_PHY_PLL_DIV_0 0x008
+#define PCIE_PHY_PLL_BIAS  0x00c
+#define PCIE_PHY_DCC_FEEDBACK  0x014
+#define PCIE_PHY_PLL_DIV_1 0x05c
+#define PCIE_PHY_COMMON_POWER  0x064
+#define PCIE_PHY_COMMON_PD_CMN BIT(3)
+#define PCIE_PHY_TRSV0_EMP_LVL 0x084
+#define PCIE_PHY_TRSV0_DRV_LVL 0x088
+#define PCIE_PHY_TRSV0_RXCDR   0x0ac
+#define PCIE_PHY_TRSV0_POWER   0x0c4
+#define PCIE_PHY_TRSV0_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV0_LVCC0x0dc
+#define PCIE_PHY_TRSV1_EMP_LVL 0x144
+#define PCIE_PHY_TRSV1_RXCDR   0x16c
+#define PCIE_PHY_TRSV1_POWER   0x184
+#define PCIE_PHY_TRSV1_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV1_LVCC0x19c
+#define PCIE_PHY_TRSV2_EMP_LVL 0x204
+#define PCIE_PHY_TRSV2_RXCDR   0x22c
+#define PCIE_PHY_TRSV2_POWER   0x244
+#define PCIE_PHY_TRSV2_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV2_LVCC0x25c
+#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
+#define PCIE_PHY_TRSV3_RXCDR   0x2ec
+#define PCIE_PHY_TRSV3_POWER   0x304
+#define PCIE_PHY_TRSV3_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV3_LVCC0x31c
+
+struct exynos_pcie_phy_data {
+   struct phy_ops  *ops;
+};
+
+/* For Exynos pcie phy */
+struct exynos_pcie_phy {
+   const struct exynos_pcie_phy_data *drv_data;
+   void __iomem *phy_base;
+   void __iomem *blk_base; /* For exynos5440 */
+};
+
+static void exynos_pcie_phy_writel(void __iomem 

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[pankaj.dubey]

Hi Jaehoon,

On Wednesday 04 January 2017 06:04 PM, Jaehoon Chung wrote:
> This patch supports to use Generic Phy framework for Exynos PCIe phy.
> When Exynos that supported the pcie want to use the PCIe,
> it needs to control the phy resgister.
> But it should be more complex to control in their own PCIe device drivers.
> 
> Currently, there is an exynos5440 case to support the pcie.
> So this driver is based on Exynos5440 PCIe.
> In future, will support the Other exynos SoCs likes exynos5433, exynos7.
> 
> Signed-off-by: Jaehoon Chung 
> ---
> Changelog on V2:
> - Not include the codes relevant to pci-exynos.
> - Remove the getting child node.
> 

Reviewed-by: Pankaj Dubey 

Thanks,
Pankaj Dubey

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[pankaj.dubey]

Hi Jaehoon,

On Wednesday 04 January 2017 06:04 PM, Jaehoon Chung wrote:
> This patch supports to use Generic Phy framework for Exynos PCIe phy.
> When Exynos that supported the pcie want to use the PCIe,
> it needs to control the phy resgister.
> But it should be more complex to control in their own PCIe device drivers.
> 
> Currently, there is an exynos5440 case to support the pcie.
> So this driver is based on Exynos5440 PCIe.
> In future, will support the Other exynos SoCs likes exynos5433, exynos7.
> 
> Signed-off-by: Jaehoon Chung 
> ---
> Changelog on V2:
> - Not include the codes relevant to pci-exynos.
> - Remove the getting child node.
> 

Reviewed-by: Pankaj Dubey 

Thanks,
Pankaj Dubey

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Jaehoon Chung]

On 01/05/2017 02:52 AM, Krzysztof Kozlowski wrote:
> On Wed, Jan 04, 2017 at 09:34:32PM +0900, Jaehoon Chung wrote:
>> This patch supports to use Generic Phy framework for Exynos PCIe phy.
>> When Exynos that supported the pcie want to use the PCIe,
>> it needs to control the phy resgister.
>> But it should be more complex to control in their own PCIe device drivers.
>>
>> Currently, there is an exynos5440 case to support the pcie.
>> So this driver is based on Exynos5440 PCIe.
>> In future, will support the Other exynos SoCs likes exynos5433, exynos7.
> 
> I have troubles understanding this. Please, work on the commit message.
> 
> For the code itself:
> Acked-by: Krzysztof Kozlowski 
> ... but commit message is really important to understand why/what was
> done.

Will update the commit-msg. Thanks for comments.

Best Regards,
Jaehoon Chung

> 
> Best regards,
> Krzysztof
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Jaehoon Chung]

On 01/05/2017 02:52 AM, Krzysztof Kozlowski wrote:
> On Wed, Jan 04, 2017 at 09:34:32PM +0900, Jaehoon Chung wrote:
>> This patch supports to use Generic Phy framework for Exynos PCIe phy.
>> When Exynos that supported the pcie want to use the PCIe,
>> it needs to control the phy resgister.
>> But it should be more complex to control in their own PCIe device drivers.
>>
>> Currently, there is an exynos5440 case to support the pcie.
>> So this driver is based on Exynos5440 PCIe.
>> In future, will support the Other exynos SoCs likes exynos5433, exynos7.
> 
> I have troubles understanding this. Please, work on the commit message.
> 
> For the code itself:
> Acked-by: Krzysztof Kozlowski 
> ... but commit message is really important to understand why/what was
> done.

Will update the commit-msg. Thanks for comments.

Best Regards,
Jaehoon Chung

> 
> Best regards,
> Krzysztof
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pci" in
> the body of a message to majord...@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 
> 

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Jingoo Han]

On Wednesday, January 4, 2017 7:35 AM, Jaehoon Chung wrote:
> 
> This patch supports to use Generic Phy framework for Exynos PCIe phy.
> When Exynos that supported the pcie want to use the PCIe,
> it needs to control the phy resgister.
> But it should be more complex to control in their own PCIe device drivers.
> 
> Currently, there is an exynos5440 case to support the pcie.
> So this driver is based on Exynos5440 PCIe.
> In future, will support the Other exynos SoCs likes exynos5433, exynos7.
> 
> Signed-off-by: Jaehoon Chung 

Reviewed-by: Jingoo Han 

Best regards,
Jingoo Han

> ---
> Changelog on V2:
> - Not include the codes relevant to pci-exynos.
> - Remove the getting child node.
> 
>  drivers/phy/Kconfig   |   9 ++
>  drivers/phy/Makefile  |   1 +
>  drivers/phy/phy-exynos-pcie.c | 280
> ++
>  3 files changed, 290 insertions(+)
>  create mode 100644 drivers/phy/phy-exynos-pcie.c
> 

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Jingoo Han]

On Wednesday, January 4, 2017 7:35 AM, Jaehoon Chung wrote:
> 
> This patch supports to use Generic Phy framework for Exynos PCIe phy.
> When Exynos that supported the pcie want to use the PCIe,
> it needs to control the phy resgister.
> But it should be more complex to control in their own PCIe device drivers.
> 
> Currently, there is an exynos5440 case to support the pcie.
> So this driver is based on Exynos5440 PCIe.
> In future, will support the Other exynos SoCs likes exynos5433, exynos7.
> 
> Signed-off-by: Jaehoon Chung 

Reviewed-by: Jingoo Han 

Best regards,
Jingoo Han

> ---
> Changelog on V2:
> - Not include the codes relevant to pci-exynos.
> - Remove the getting child node.
> 
>  drivers/phy/Kconfig   |   9 ++
>  drivers/phy/Makefile  |   1 +
>  drivers/phy/phy-exynos-pcie.c | 280
> ++
>  3 files changed, 290 insertions(+)
>  create mode 100644 drivers/phy/phy-exynos-pcie.c
> 

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Krzysztof Kozlowski]

On Wed, Jan 04, 2017 at 09:34:32PM +0900, Jaehoon Chung wrote:
> This patch supports to use Generic Phy framework for Exynos PCIe phy.
> When Exynos that supported the pcie want to use the PCIe,
> it needs to control the phy resgister.
> But it should be more complex to control in their own PCIe device drivers.
> 
> Currently, there is an exynos5440 case to support the pcie.
> So this driver is based on Exynos5440 PCIe.
> In future, will support the Other exynos SoCs likes exynos5433, exynos7.

I have troubles understanding this. Please, work on the commit message.

For the code itself:
Acked-by: Krzysztof Kozlowski 
... but commit message is really important to understand why/what was
done.

Best regards,
Krzysztof

Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Krzysztof Kozlowski]

On Wed, Jan 04, 2017 at 09:34:32PM +0900, Jaehoon Chung wrote:
> This patch supports to use Generic Phy framework for Exynos PCIe phy.
> When Exynos that supported the pcie want to use the PCIe,
> it needs to control the phy resgister.
> But it should be more complex to control in their own PCIe device drivers.
> 
> Currently, there is an exynos5440 case to support the pcie.
> So this driver is based on Exynos5440 PCIe.
> In future, will support the Other exynos SoCs likes exynos5433, exynos7.

I have troubles understanding this. Please, work on the commit message.

For the code itself:
Acked-by: Krzysztof Kozlowski 
... but commit message is really important to understand why/what was
done.

Best regards,
Krzysztof

[PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Jaehoon Chung]

This patch supports to use Generic Phy framework for Exynos PCIe phy.
When Exynos that supported the pcie want to use the PCIe,
it needs to control the phy resgister.
But it should be more complex to control in their own PCIe device drivers.

Currently, there is an exynos5440 case to support the pcie.
So this driver is based on Exynos5440 PCIe.
In future, will support the Other exynos SoCs likes exynos5433, exynos7.

Signed-off-by: Jaehoon Chung 
---
Changelog on V2:
- Not include the codes relevant to pci-exynos.
- Remove the getting child node.

 drivers/phy/Kconfig   |   9 ++
 drivers/phy/Makefile  |   1 +
 drivers/phy/phy-exynos-pcie.c | 280 ++
 3 files changed, 290 insertions(+)
 create mode 100644 drivers/phy/phy-exynos-pcie.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e8eb7f2..2dddef4 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
  This driver provides PHY interface for USB 3.0 DRD controller
  present on Exynos5 SoC series.
 
+config PHY_EXYNOS_PCIE
+   bool "Exynos PCIe PHY driver"
+   depends on ARCH_EXYNOS && OF
+   depends on PCI_EXYNOS
+   select GENERIC_PHY
+   help
+ Enable PCIe PHY support for Exynos SoC series.
+ This driver provides PHY interface for Exynos PCIe controller.
+
 config PHY_PISTACHIO_USB
tristate "IMG Pistachio USB2.0 PHY driver"
depends on MACH_PISTACHIO
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 65eb2f4..081aeb4 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += 
phy-exynos4x12-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)  += phy-exynos5250-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)   += phy-exynos5-usbdrd.o
+obj-$(CONFIG_PHY_EXYNOS_PCIE)  += phy-exynos-pcie.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)   += phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
new file mode 100644
index 000..b57f49b
--- /dev/null
+++ b/drivers/phy/phy-exynos-pcie.c
@@ -0,0 +1,280 @@
+/*
+ * Samsung EXYNOS SoC series PCIe PHY driver
+ *
+ * Phy provider for PCIe controller on Exynos SoC series
+ *
+ * Copyright (C) 2016 Samsung Electronics Co., Ltd.
+ * Jaehoon Chung 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PCIe Purple registers */
+#define PCIE_PHY_GLOBAL_RESET  0x000
+#define PCIE_PHY_COMMON_RESET  0x004
+#define PCIE_PHY_CMN_REG   0x008
+#define PCIE_PHY_MAC_RESET 0x00c
+#define PCIE_PHY_PLL_LOCKED0x010
+#define PCIE_PHY_TRSVREG_RESET 0x020
+#define PCIE_PHY_TRSV_RESET0x024
+
+/* PCIe PHY registers */
+#define PCIE_PHY_IMPEDANCE 0x004
+#define PCIE_PHY_PLL_DIV_0 0x008
+#define PCIE_PHY_PLL_BIAS  0x00c
+#define PCIE_PHY_DCC_FEEDBACK  0x014
+#define PCIE_PHY_PLL_DIV_1 0x05c
+#define PCIE_PHY_COMMON_POWER  0x064
+#define PCIE_PHY_COMMON_PD_CMN BIT(3)
+#define PCIE_PHY_TRSV0_EMP_LVL 0x084
+#define PCIE_PHY_TRSV0_DRV_LVL 0x088
+#define PCIE_PHY_TRSV0_RXCDR   0x0ac
+#define PCIE_PHY_TRSV0_POWER   0x0c4
+#define PCIE_PHY_TRSV0_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV0_LVCC0x0dc
+#define PCIE_PHY_TRSV1_EMP_LVL 0x144
+#define PCIE_PHY_TRSV1_RXCDR   0x16c
+#define PCIE_PHY_TRSV1_POWER   0x184
+#define PCIE_PHY_TRSV1_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV1_LVCC0x19c
+#define PCIE_PHY_TRSV2_EMP_LVL 0x204
+#define PCIE_PHY_TRSV2_RXCDR   0x22c
+#define PCIE_PHY_TRSV2_POWER   0x244
+#define PCIE_PHY_TRSV2_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV2_LVCC0x25c
+#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
+#define PCIE_PHY_TRSV3_RXCDR   0x2ec
+#define PCIE_PHY_TRSV3_POWER   0x304
+#define PCIE_PHY_TRSV3_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV3_LVCC0x31c
+
+struct exynos_pcie_phy_data {
+   struct phy_ops  *ops;
+};
+
+/* For Exynos pcie phy */
+struct exynos_pcie_phy {
+   const struct exynos_pcie_phy_data *drv_data;
+   void __iomem *phy_base;
+   void __iomem *blk_base; /* For exynos5440 */
+};
+
+static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
+{
+   writel(val, base + offset);
+}
+
+static u32 

[PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy

[Jaehoon Chung]

This patch supports to use Generic Phy framework for Exynos PCIe phy.
When Exynos that supported the pcie want to use the PCIe,
it needs to control the phy resgister.
But it should be more complex to control in their own PCIe device drivers.

Currently, there is an exynos5440 case to support the pcie.
So this driver is based on Exynos5440 PCIe.
In future, will support the Other exynos SoCs likes exynos5433, exynos7.

Signed-off-by: Jaehoon Chung 
---
Changelog on V2:
- Not include the codes relevant to pci-exynos.
- Remove the getting child node.

 drivers/phy/Kconfig   |   9 ++
 drivers/phy/Makefile  |   1 +
 drivers/phy/phy-exynos-pcie.c | 280 ++
 3 files changed, 290 insertions(+)
 create mode 100644 drivers/phy/phy-exynos-pcie.c

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e8eb7f2..2dddef4 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
  This driver provides PHY interface for USB 3.0 DRD controller
  present on Exynos5 SoC series.
 
+config PHY_EXYNOS_PCIE
+   bool "Exynos PCIe PHY driver"
+   depends on ARCH_EXYNOS && OF
+   depends on PCI_EXYNOS
+   select GENERIC_PHY
+   help
+ Enable PCIe PHY support for Exynos SoC series.
+ This driver provides PHY interface for Exynos PCIe controller.
+
 config PHY_PISTACHIO_USB
tristate "IMG Pistachio USB2.0 PHY driver"
depends on MACH_PISTACHIO
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 65eb2f4..081aeb4 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += 
phy-exynos4x12-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2)  += phy-exynos5250-usb2.o
 phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
 obj-$(CONFIG_PHY_EXYNOS5_USBDRD)   += phy-exynos5-usbdrd.o
+obj-$(CONFIG_PHY_EXYNOS_PCIE)  += phy-exynos-pcie.o
 obj-$(CONFIG_PHY_QCOM_APQ8064_SATA)+= phy-qcom-apq8064-sata.o
 obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
 obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2)   += phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
new file mode 100644
index 000..b57f49b
--- /dev/null
+++ b/drivers/phy/phy-exynos-pcie.c
@@ -0,0 +1,280 @@
+/*
+ * Samsung EXYNOS SoC series PCIe PHY driver
+ *
+ * Phy provider for PCIe controller on Exynos SoC series
+ *
+ * Copyright (C) 2016 Samsung Electronics Co., Ltd.
+ * Jaehoon Chung 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* PCIe Purple registers */
+#define PCIE_PHY_GLOBAL_RESET  0x000
+#define PCIE_PHY_COMMON_RESET  0x004
+#define PCIE_PHY_CMN_REG   0x008
+#define PCIE_PHY_MAC_RESET 0x00c
+#define PCIE_PHY_PLL_LOCKED0x010
+#define PCIE_PHY_TRSVREG_RESET 0x020
+#define PCIE_PHY_TRSV_RESET0x024
+
+/* PCIe PHY registers */
+#define PCIE_PHY_IMPEDANCE 0x004
+#define PCIE_PHY_PLL_DIV_0 0x008
+#define PCIE_PHY_PLL_BIAS  0x00c
+#define PCIE_PHY_DCC_FEEDBACK  0x014
+#define PCIE_PHY_PLL_DIV_1 0x05c
+#define PCIE_PHY_COMMON_POWER  0x064
+#define PCIE_PHY_COMMON_PD_CMN BIT(3)
+#define PCIE_PHY_TRSV0_EMP_LVL 0x084
+#define PCIE_PHY_TRSV0_DRV_LVL 0x088
+#define PCIE_PHY_TRSV0_RXCDR   0x0ac
+#define PCIE_PHY_TRSV0_POWER   0x0c4
+#define PCIE_PHY_TRSV0_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV0_LVCC0x0dc
+#define PCIE_PHY_TRSV1_EMP_LVL 0x144
+#define PCIE_PHY_TRSV1_RXCDR   0x16c
+#define PCIE_PHY_TRSV1_POWER   0x184
+#define PCIE_PHY_TRSV1_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV1_LVCC0x19c
+#define PCIE_PHY_TRSV2_EMP_LVL 0x204
+#define PCIE_PHY_TRSV2_RXCDR   0x22c
+#define PCIE_PHY_TRSV2_POWER   0x244
+#define PCIE_PHY_TRSV2_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV2_LVCC0x25c
+#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
+#define PCIE_PHY_TRSV3_RXCDR   0x2ec
+#define PCIE_PHY_TRSV3_POWER   0x304
+#define PCIE_PHY_TRSV3_PD_TSV  BIT(7)
+#define PCIE_PHY_TRSV3_LVCC0x31c
+
+struct exynos_pcie_phy_data {
+   struct phy_ops  *ops;
+};
+
+/* For Exynos pcie phy */
+struct exynos_pcie_phy {
+   const struct exynos_pcie_phy_data *drv_data;
+   void __iomem *phy_base;
+   void __iomem *blk_base; /* For exynos5440 */
+};
+
+static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
+{
+   writel(val, base + offset);
+}
+
+static u32 exynos_pcie_phy_readl(void __iomem *base, u32