Re: [PATCH V2 3/3] arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support

2019-06-03 Thread Abel Vesa 
On 19-06-03 09:27:47, anson.hu...@nxp.com wrote:
> From: Anson Huang 
> 
> This patch adds basic i.MM8MN DDR4 EVK board support.
> 
> Signed-off-by: Anson Huang 
> ---
> No changes.
> ---
>  arch/arm64/boot/dts/freescale/Makefile|   1 +
>  arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 217 
> ++
>  2 files changed, 218 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> 
> diff --git a/arch/arm64/boot/dts/freescale/Makefile 
> b/arch/arm64/boot/dts/freescale/Makefile
> index 0bd122f..2cdd4cc 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -20,6 +20,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
>  dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
>  
> +dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb

Nitpick: Move this bellow imx8mm-evk.dtb to keep them alphabetically ordered.

>  dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts 
> b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> new file mode 100644
> index 000..da552c2
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> @@ -0,0 +1,217 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2019 NXP
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8mn.dtsi"
> +
> +/ {
> + model = "NXP i.MX8MNano DDR4 EVK board";
> + compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
> +
> + chosen {
> + stdout-path = &uart2;
> + };
> +
> + reg_usdhc2_vmmc: regulator-usdhc2 {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
> + regulator-name = "VSD_3V3";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> +
> + pinctrl_fec1: fec1grp {
> + fsl,pins = <
> + MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> + MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO   0x3
> + MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
> + MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
> + MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
> + MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
> + MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
> + MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
> + MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
> + MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
> + MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
> + MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
> + MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> + MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> + MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO220x19
> + >;
> + };
> +
> + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
> + fsl,pins = <
> + MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
> + MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
> + >;
> + };
> +
> + pinctrl_usdhc2_gpio: usdhc2grpgpio {
> + fsl,pins = <
> + MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15  0x1c4
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
> + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
> + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
> + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
> + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
> + MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
> + MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
> + >;
> + };
> +
> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> + fsl,pins = <
> + MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
> + MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
> + MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
> + MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
> + MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
> +

[PATCH V2 3/3] arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support

2019-06-02 Thread Anson . Huang 
From: Anson Huang 

This patch adds basic i.MM8MN DDR4 EVK board support.

Signed-off-by: Anson Huang 
---
No changes.
---
 arch/arm64/boot/dts/freescale/Makefile|   1 +
 arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 217 ++
 2 files changed, 218 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts

diff --git a/arch/arm64/boot/dts/freescale/Makefile 
b/arch/arm64/boot/dts/freescale/Makefile
index 0bd122f..2cdd4cc 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -20,6 +20,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
 
+dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts 
b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
new file mode 100644
index 000..da552c2
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8mn.dtsi"
+
+/ {
+   model = "NXP i.MX8MNano DDR4 EVK board";
+   compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
+
+   chosen {
+   stdout-path = &uart2;
+   };
+
+   reg_usdhc2_vmmc: regulator-usdhc2 {
+   compatible = "regulator-fixed";
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+   regulator-name = "VSD_3V3";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+};
+
+&iomuxc {
+   pinctrl-names = "default";
+
+   pinctrl_fec1: fec1grp {
+   fsl,pins = <
+   MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+   MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO   0x3
+   MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
+   MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
+   MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
+   MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
+   MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
+   MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
+   MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
+   MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
+   MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
+   MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
+   MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+   MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+   MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO220x19
+   >;
+   };
+
+   pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+   fsl,pins = <
+   MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+   >;
+   };
+
+   pinctrl_uart2: uart2grp {
+   fsl,pins = <
+   MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+   MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+   >;
+   };
+
+   pinctrl_usdhc2_gpio: usdhc2grpgpio {
+   fsl,pins = <
+   MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15  0x1c4
+   >;
+   };
+
+   pinctrl_usdhc2: usdhc2grp {
+   fsl,pins = <
+   MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
+   MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
+   MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
+   MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
+   MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
+   MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
+   MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+   >;
+   };
+
+   pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+   fsl,pins = <
+   MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
+   MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
+   MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
+   MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
+   MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
+   MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
+   MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT  0x1d0
+   >;
+   };
+
+   pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+   fsl,pins = <
+