Re: [PATCH V3] clk: Add composite clock type

[Mike Turquette]

Quoting Prashant Gaikwad (2013-03-20 05:00:34)
> Not all clocks are required to be decomposed into basic clock
> types but at the same time want to use the functionality
> provided by these basic clock types instead of duplicating.
> 
> For example, Tegra SoC has ~100 clocks which can be decomposed
> into Mux -> Div -> Gate clock types making the clock count to
> ~300. Also, parent change operation can not be performed on gate
> clock which forces to use mux clock in driver if want to change
> the parent.
> 
> Instead aggregate the basic clock types functionality into one
> clock and just use this clock for all operations. This clock
> type re-uses the functionality of basic clock types and not
> limited to basic clock types but any hardware-specific
> implementation.
> 
> Signed-off-by: Prashant Gaikwad 

This version looks cleaner.  Thanks for the respin.  Taken into
clk-next.

Regards,
Mike

> ---
> 
> Changes from V2:
> - Move clk_ops inside clk_composite instead of dynamically allocation.
> 
> ---
>  drivers/clk/Makefile |1 +
>  drivers/clk/clk-composite.c  |  201 
> ++
>  include/linux/clk-provider.h |   31 +++
>  3 files changed, 233 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/clk/clk-composite.c
> 
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index 0147022..097ed01 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)+= clk-fixed-factor.o
>  obj-$(CONFIG_COMMON_CLK)   += clk-fixed-rate.o
>  obj-$(CONFIG_COMMON_CLK)   += clk-gate.o
>  obj-$(CONFIG_COMMON_CLK)   += clk-mux.o
> +obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
>  
>  # SoCs specific
>  obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
> diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
> new file mode 100644
> index 000..097dee4
> --- /dev/null
> +++ b/drivers/clk/clk-composite.c
> @@ -0,0 +1,201 @@
> +/*
> + * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see .
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
> +
> +static u8 clk_composite_get_parent(struct clk_hw *hw)
> +{
> +   struct clk_composite *composite = to_clk_composite(hw);
> +   const struct clk_ops *mux_ops = composite->mux_ops;
> +   struct clk_hw *mux_hw = composite->mux_hw;
> +
> +   mux_hw->clk = hw->clk;
> +
> +   return mux_ops->get_parent(mux_hw);
> +}
> +
> +static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
> +{
> +   struct clk_composite *composite = to_clk_composite(hw);
> +   const struct clk_ops *mux_ops = composite->mux_ops;
> +   struct clk_hw *mux_hw = composite->mux_hw;
> +
> +   mux_hw->clk = hw->clk;
> +
> +   return mux_ops->set_parent(mux_hw, index);
> +}
> +
> +static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
> +   unsigned long parent_rate)
> +{
> +   struct clk_composite *composite = to_clk_composite(hw);
> +   const struct clk_ops *div_ops = composite->div_ops;
> +   struct clk_hw *div_hw = composite->div_hw;
> +
> +   div_hw->clk = hw->clk;
> +
> +   return div_ops->recalc_rate(div_hw, parent_rate);
> +}
> +
> +static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *prate)
> +{
> +   struct clk_composite *composite = to_clk_composite(hw);
> +   const struct clk_ops *div_ops = composite->div_ops;
> +   struct clk_hw *div_hw = composite->div_hw;
> +
> +   div_hw->clk = hw->clk;
> +
> +   return div_ops->round_rate(div_hw, rate, prate);
> +}
> +
> +static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
> +  unsigned long parent_rate)
> +{
> +   struct clk_composite *composite = to_clk_composite(hw);
> +   const struct clk_ops *div_ops = composite->div_ops;
> +   struct clk_hw *div_hw = composite->div_hw;
> +
> +   div_hw->clk = hw->clk;
> +
> +   return div_ops->set_rate(div_hw, rate, parent_rate);
> +}
> +
> +static int clk_composite_is_enabled(struct clk_hw *hw)
> +{
> +   struct clk_composite *composite = to_clk_composite(hw);
> +   const struct 

Re: [PATCH V3] clk: Add composite clock type

[Prashant Gaikwad]

Mike,

Please merge this patch.

Thanks & Regards,
PrashantG

On Wednesday 20 March 2013 05:30 PM, Prashant Gaikwad wrote:

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad 
---

Changes from V2:
- Move clk_ops inside clk_composite instead of dynamically allocation.

---
  drivers/clk/Makefile |1 +
  drivers/clk/clk-composite.c  |  201 ++
  include/linux/clk-provider.h |   31 +++
  3 files changed, 233 insertions(+), 0 deletions(-)
  create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0147022..097ed01 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)+= clk-fixed-factor.o
  obj-$(CONFIG_COMMON_CLK)  += clk-fixed-rate.o
  obj-$(CONFIG_COMMON_CLK)  += clk-gate.o
  obj-$(CONFIG_COMMON_CLK)  += clk-mux.o
+obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
  
  # SoCs specific

  obj-$(CONFIG_ARCH_BCM2835)+= clk-bcm2835.o
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 000..097dee4
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite->mux_ops;
+   struct clk_hw *mux_hw = composite->mux_hw;
+
+   mux_hw->clk = hw->clk;
+
+   return mux_ops->get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite->mux_ops;
+   struct clk_hw *mux_hw = composite->mux_hw;
+
+   mux_hw->clk = hw->clk;
+
+   return mux_ops->set_parent(mux_hw, index);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite->div_ops;
+   struct clk_hw *div_hw = composite->div_hw;
+
+   div_hw->clk = hw->clk;
+
+   return div_ops->recalc_rate(div_hw, parent_rate);
+}
+
+static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite->div_ops;
+   struct clk_hw *div_hw = composite->div_hw;
+
+   div_hw->clk = hw->clk;
+
+   return div_ops->round_rate(div_hw, rate, prate);
+}
+
+static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
+  unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite->div_ops;
+   struct clk_hw *div_hw = composite->div_hw;
+
+   div_hw->clk = hw->clk;
+
+   return div_ops->set_rate(div_hw, rate, parent_rate);
+}
+
+static int clk_composite_is_enabled(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *gate_ops = composite->gate_ops;
+   struct clk_hw *gate_hw = composite->gate_hw;
+
+   gate_hw->clk = hw->clk;
+
+   return gate_ops->is_enabled(gate_hw);
+}
+
+static int clk_composite_enable(struct clk_hw *hw)
+{
+   struct clk_composite *composite 

Re: [PATCH V3] clk: Add composite clock type

[Prashant Gaikwad]

Mike,

Please merge this patch.

Thanks  Regards,
PrashantG

On Wednesday 20 March 2013 05:30 PM, Prashant Gaikwad wrote:

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux - Div - Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---

Changes from V2:
- Move clk_ops inside clk_composite instead of dynamically allocation.

---
  drivers/clk/Makefile |1 +
  drivers/clk/clk-composite.c  |  201 ++
  include/linux/clk-provider.h |   31 +++
  3 files changed, 233 insertions(+), 0 deletions(-)
  create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0147022..097ed01 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)+= clk-fixed-factor.o
  obj-$(CONFIG_COMMON_CLK)  += clk-fixed-rate.o
  obj-$(CONFIG_COMMON_CLK)  += clk-gate.o
  obj-$(CONFIG_COMMON_CLK)  += clk-mux.o
+obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
  
  # SoCs specific

  obj-$(CONFIG_ARCH_BCM2835)+= clk-bcm2835.o
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 000..097dee4
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see http://www.gnu.org/licenses/.
+ */
+
+#include linux/clk.h
+#include linux/clk-provider.h
+#include linux/err.h
+#include linux/slab.h
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite-mux_ops;
+   struct clk_hw *mux_hw = composite-mux_hw;
+
+   mux_hw-clk = hw-clk;
+
+   return mux_ops-get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite-mux_ops;
+   struct clk_hw *mux_hw = composite-mux_hw;
+
+   mux_hw-clk = hw-clk;
+
+   return mux_ops-set_parent(mux_hw, index);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite-div_ops;
+   struct clk_hw *div_hw = composite-div_hw;
+
+   div_hw-clk = hw-clk;
+
+   return div_ops-recalc_rate(div_hw, parent_rate);
+}
+
+static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite-div_ops;
+   struct clk_hw *div_hw = composite-div_hw;
+
+   div_hw-clk = hw-clk;
+
+   return div_ops-round_rate(div_hw, rate, prate);
+}
+
+static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
+  unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite-div_ops;
+   struct clk_hw *div_hw = composite-div_hw;
+
+   div_hw-clk = hw-clk;
+
+   return div_ops-set_rate(div_hw, rate, parent_rate);
+}
+
+static int clk_composite_is_enabled(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *gate_ops = composite-gate_ops;
+   struct clk_hw *gate_hw = composite-gate_hw;
+
+   gate_hw-clk = hw-clk;
+
+   return gate_ops-is_enabled(gate_hw);
+}
+
+static int clk_composite_enable(struct clk_hw *hw)
+{
+  

Re: [PATCH V3] clk: Add composite clock type

[Mike Turquette]

Quoting Prashant Gaikwad (2013-03-20 05:00:34)
 Not all clocks are required to be decomposed into basic clock
 types but at the same time want to use the functionality
 provided by these basic clock types instead of duplicating.
 
 For example, Tegra SoC has ~100 clocks which can be decomposed
 into Mux - Div - Gate clock types making the clock count to
 ~300. Also, parent change operation can not be performed on gate
 clock which forces to use mux clock in driver if want to change
 the parent.
 
 Instead aggregate the basic clock types functionality into one
 clock and just use this clock for all operations. This clock
 type re-uses the functionality of basic clock types and not
 limited to basic clock types but any hardware-specific
 implementation.
 
 Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com

This version looks cleaner.  Thanks for the respin.  Taken into
clk-next.

Regards,
Mike

 ---
 
 Changes from V2:
 - Move clk_ops inside clk_composite instead of dynamically allocation.
 
 ---
  drivers/clk/Makefile |1 +
  drivers/clk/clk-composite.c  |  201 
 ++
  include/linux/clk-provider.h |   31 +++
  3 files changed, 233 insertions(+), 0 deletions(-)
  create mode 100644 drivers/clk/clk-composite.c
 
 diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
 index 0147022..097ed01 100644
 --- a/drivers/clk/Makefile
 +++ b/drivers/clk/Makefile
 @@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)+= clk-fixed-factor.o
  obj-$(CONFIG_COMMON_CLK)   += clk-fixed-rate.o
  obj-$(CONFIG_COMMON_CLK)   += clk-gate.o
  obj-$(CONFIG_COMMON_CLK)   += clk-mux.o
 +obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
  
  # SoCs specific
  obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
 diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
 new file mode 100644
 index 000..097dee4
 --- /dev/null
 +++ b/drivers/clk/clk-composite.c
 @@ -0,0 +1,201 @@
 +/*
 + * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
 + *
 + * This program is free software; you can redistribute it and/or modify it
 + * under the terms and conditions of the GNU General Public License,
 + * version 2, as published by the Free Software Foundation.
 + *
 + * This program is distributed in the hope it will be useful, but WITHOUT
 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 + * more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program.  If not, see http://www.gnu.org/licenses/.
 + */
 +
 +#include linux/clk.h
 +#include linux/clk-provider.h
 +#include linux/err.h
 +#include linux/slab.h
 +
 +#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
 +
 +static u8 clk_composite_get_parent(struct clk_hw *hw)
 +{
 +   struct clk_composite *composite = to_clk_composite(hw);
 +   const struct clk_ops *mux_ops = composite-mux_ops;
 +   struct clk_hw *mux_hw = composite-mux_hw;
 +
 +   mux_hw-clk = hw-clk;
 +
 +   return mux_ops-get_parent(mux_hw);
 +}
 +
 +static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
 +{
 +   struct clk_composite *composite = to_clk_composite(hw);
 +   const struct clk_ops *mux_ops = composite-mux_ops;
 +   struct clk_hw *mux_hw = composite-mux_hw;
 +
 +   mux_hw-clk = hw-clk;
 +
 +   return mux_ops-set_parent(mux_hw, index);
 +}
 +
 +static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
 +   unsigned long parent_rate)
 +{
 +   struct clk_composite *composite = to_clk_composite(hw);
 +   const struct clk_ops *div_ops = composite-div_ops;
 +   struct clk_hw *div_hw = composite-div_hw;
 +
 +   div_hw-clk = hw-clk;
 +
 +   return div_ops-recalc_rate(div_hw, parent_rate);
 +}
 +
 +static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
 + unsigned long *prate)
 +{
 +   struct clk_composite *composite = to_clk_composite(hw);
 +   const struct clk_ops *div_ops = composite-div_ops;
 +   struct clk_hw *div_hw = composite-div_hw;
 +
 +   div_hw-clk = hw-clk;
 +
 +   return div_ops-round_rate(div_hw, rate, prate);
 +}
 +
 +static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
 +  unsigned long parent_rate)
 +{
 +   struct clk_composite *composite = to_clk_composite(hw);
 +   const struct clk_ops *div_ops = composite-div_ops;
 +   struct clk_hw *div_hw = composite-div_hw;
 +
 +   div_hw-clk = hw-clk;
 +
 +   return div_ops-set_rate(div_hw, rate, parent_rate);
 +}
 +
 +static int clk_composite_is_enabled(struct clk_hw *hw)
 +{
 +   struct clk_composite *composite = to_clk_composite(hw);
 +   const struct clk_ops *gate_ops = composite-gate_ops;
 +   struct clk_hw *gate_hw = composite-gate_hw;
 

[PATCH V3] clk: Add composite clock type

[Prashant Gaikwad]

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad 
---

Changes from V2:
- Move clk_ops inside clk_composite instead of dynamically allocation.

---
 drivers/clk/Makefile |1 +
 drivers/clk/clk-composite.c  |  201 ++
 include/linux/clk-provider.h |   31 +++
 3 files changed, 233 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0147022..097ed01 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)+= clk-fixed-factor.o
 obj-$(CONFIG_COMMON_CLK)   += clk-fixed-rate.o
 obj-$(CONFIG_COMMON_CLK)   += clk-gate.o
 obj-$(CONFIG_COMMON_CLK)   += clk-mux.o
+obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
 
 # SoCs specific
 obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 000..097dee4
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite->mux_ops;
+   struct clk_hw *mux_hw = composite->mux_hw;
+
+   mux_hw->clk = hw->clk;
+
+   return mux_ops->get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite->mux_ops;
+   struct clk_hw *mux_hw = composite->mux_hw;
+
+   mux_hw->clk = hw->clk;
+
+   return mux_ops->set_parent(mux_hw, index);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite->div_ops;
+   struct clk_hw *div_hw = composite->div_hw;
+
+   div_hw->clk = hw->clk;
+
+   return div_ops->recalc_rate(div_hw, parent_rate);
+}
+
+static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite->div_ops;
+   struct clk_hw *div_hw = composite->div_hw;
+
+   div_hw->clk = hw->clk;
+
+   return div_ops->round_rate(div_hw, rate, prate);
+}
+
+static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
+  unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite->div_ops;
+   struct clk_hw *div_hw = composite->div_hw;
+
+   div_hw->clk = hw->clk;
+
+   return div_ops->set_rate(div_hw, rate, parent_rate);
+}
+
+static int clk_composite_is_enabled(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *gate_ops = composite->gate_ops;
+   struct clk_hw *gate_hw = composite->gate_hw;
+
+   gate_hw->clk = hw->clk;
+
+   return gate_ops->is_enabled(gate_hw);
+}
+
+static int clk_composite_enable(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *gate_ops = composite->gate_ops;
+   struct clk_hw *gate_hw = 

[PATCH V3] clk: Add composite clock type

[Prashant Gaikwad]

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux - Div - Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad pgaik...@nvidia.com
---

Changes from V2:
- Move clk_ops inside clk_composite instead of dynamically allocation.

---
 drivers/clk/Makefile |1 +
 drivers/clk/clk-composite.c  |  201 ++
 include/linux/clk-provider.h |   31 +++
 3 files changed, 233 insertions(+), 0 deletions(-)
 create mode 100644 drivers/clk/clk-composite.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 0147022..097ed01 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK)+= clk-fixed-factor.o
 obj-$(CONFIG_COMMON_CLK)   += clk-fixed-rate.o
 obj-$(CONFIG_COMMON_CLK)   += clk-gate.o
 obj-$(CONFIG_COMMON_CLK)   += clk-mux.o
+obj-$(CONFIG_COMMON_CLK)   += clk-composite.o
 
 # SoCs specific
 obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
new file mode 100644
index 000..097dee4
--- /dev/null
+++ b/drivers/clk/clk-composite.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2013 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see http://www.gnu.org/licenses/.
+ */
+
+#include linux/clk.h
+#include linux/clk-provider.h
+#include linux/err.h
+#include linux/slab.h
+
+#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+
+static u8 clk_composite_get_parent(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite-mux_ops;
+   struct clk_hw *mux_hw = composite-mux_hw;
+
+   mux_hw-clk = hw-clk;
+
+   return mux_ops-get_parent(mux_hw);
+}
+
+static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *mux_ops = composite-mux_ops;
+   struct clk_hw *mux_hw = composite-mux_hw;
+
+   mux_hw-clk = hw-clk;
+
+   return mux_ops-set_parent(mux_hw, index);
+}
+
+static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
+   unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite-div_ops;
+   struct clk_hw *div_hw = composite-div_hw;
+
+   div_hw-clk = hw-clk;
+
+   return div_ops-recalc_rate(div_hw, parent_rate);
+}
+
+static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite-div_ops;
+   struct clk_hw *div_hw = composite-div_hw;
+
+   div_hw-clk = hw-clk;
+
+   return div_ops-round_rate(div_hw, rate, prate);
+}
+
+static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
+  unsigned long parent_rate)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *div_ops = composite-div_ops;
+   struct clk_hw *div_hw = composite-div_hw;
+
+   div_hw-clk = hw-clk;
+
+   return div_ops-set_rate(div_hw, rate, parent_rate);
+}
+
+static int clk_composite_is_enabled(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *gate_ops = composite-gate_ops;
+   struct clk_hw *gate_hw = composite-gate_hw;
+
+   gate_hw-clk = hw-clk;
+
+   return gate_ops-is_enabled(gate_hw);
+}
+
+static int clk_composite_enable(struct clk_hw *hw)
+{
+   struct clk_composite *composite = to_clk_composite(hw);
+   const struct clk_ops *gate_ops = composite-gate_ops;
+