Re: [PATCH V3 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN in non-coherent DMA mode

[Andrew Morton]

On Wed, 13 Sep 2017 17:20:51 +0800 Huacai Chen  wrote:

> In non-coherent DMA mode, kernel uses cache flushing operations to
> maintain I/O coherency, so the dmapool objects should be aligned to
> ARCH_DMA_MINALIGN.

What are the user-visible effects of this bug?

[PATCH V3 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN in non-coherent DMA mode

[Huacai Chen]

In non-coherent DMA mode, kernel uses cache flushing operations to
maintain I/O coherency, so the dmapool objects should be aligned to
ARCH_DMA_MINALIGN.

Cc: sta...@vger.kernel.org
Signed-off-by: Huacai Chen 
---
 mm/dmapool.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/mm/dmapool.c b/mm/dmapool.c
index 4d90a64..2ac6f4a 100644
--- a/mm/dmapool.c
+++ b/mm/dmapool.c
@@ -140,6 +140,9 @@ struct dma_pool *dma_pool_create(const char *name, struct 
device *dev,
else if (align & (align - 1))
return NULL;
 
+   if (!plat_device_is_coherent(dev))
+   align = max_t(size_t, align, dma_get_cache_alignment());
+
if (size == 0)
return NULL;
else if (size < 4)
-- 
2.7.0