Re: [PATCH V3 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN innon-coherent DMA mode
Hi, Andrew, It will cause data corruption, at least on MIPS: step 1, dma_map_single step 2, cache_invalidate (no writeback) step 3, dma_from_device step 4, dma_unmap_single If a DMA buffer and a kernel structure share a same cache line, and if the kernel structure has dirty data, cache_invalidate (no writeback) may cause data lost. Huacai -- Original -- From: "Andrew Morton"<a...@linux-foundation.org>; Date: Thu, Sep 14, 2017 05:52 AM To: "Huacai Chen"<che...@lemote.com>; Cc: "Fuxin Zhang"<zhan...@lemote.com>; "linux-mm"<linux...@kvack.org>; "linux-kernel"<linux-kernel@vger.kernel.org>; "stable"<sta...@vger.kernel.org>; Subject: Re: [PATCH V3 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN innon-coherent DMA mode On Wed, 13 Sep 2017 17:20:51 +0800 Huacai Chen <che...@lemote.com> wrote: > In non-coherent DMA mode, kernel uses cache flushing operations to > maintain I/O coherency, so the dmapool objects should be aligned to > ARCH_DMA_MINALIGN. What are the user-visible effects of this bug?
Re: [PATCH V3 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN innon-coherent DMA mode
Hi, Andrew, It will cause data corruption, at least on MIPS: step 1, dma_map_single step 2, cache_invalidate (no writeback) step 3, dma_from_device step 4, dma_unmap_single If a DMA buffer and a kernel structure share a same cache line, and if the kernel structure has dirty data, cache_invalidate (no writeback) may cause data lost. Huacai -- Original -- From: "Andrew Morton"; Date: Thu, Sep 14, 2017 05:52 AM To: "Huacai Chen"; Cc: "Fuxin Zhang"; "linux-mm"; "linux-kernel"; "stable"; Subject: Re: [PATCH V3 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN innon-coherent DMA mode On Wed, 13 Sep 2017 17:20:51 +0800 Huacai Chen wrote: > In non-coherent DMA mode, kernel uses cache flushing operations to > maintain I/O coherency, so the dmapool objects should be aligned to > ARCH_DMA_MINALIGN. What are the user-visible effects of this bug?
