Re: [PATCH V3 7/8] clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLE

2016-07-01 Thread Stephen Boyd 
On 06/30, Dong Aisheng wrote:
> i.MX7D requires all clocks operations including enable/disable,
> rate change and re-parent with its parent clock on.
> Changing to the correct APIs to tell clk core such requirement.
> 
> Cc: Michael Turquette 
> Cc: Stephen Boyd 
> Cc: Shawn Guo 
> Signed-off-by: Dong Aisheng 
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH V3 7/8] clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLE

2016-07-01 Thread Stephen Boyd 
On 06/30, Dong Aisheng wrote:
> i.MX7D requires all clocks operations including enable/disable,
> rate change and re-parent with its parent clock on.
> Changing to the correct APIs to tell clk core such requirement.
> 
> Cc: Michael Turquette 
> Cc: Stephen Boyd 
> Cc: Shawn Guo 
> Signed-off-by: Dong Aisheng 
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH V3 7/8] clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLE

2016-06-30 Thread Dong Aisheng 
i.MX7D requires all clocks operations including enable/disable,
rate change and re-parent with its parent clock on.
Changing to the correct APIs to tell clk core such requirement.

Cc: Michael Turquette 
Cc: Stephen Boyd 
Cc: Shawn Guo 
Signed-off-by: Dong Aisheng 
---
 drivers/clk/imx/clk-imx7d.c | 714 ++--
 1 file changed, 357 insertions(+), 357 deletions(-)

diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 522996800d5b..bb5affae0850 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -474,363 +474,363 @@ static void __init imx7d_clocks_init(struct device_node 
*ccm_node)
base = of_iomap(np, 0);
WARN_ON(!base);
 
-   clks[IMX7D_ARM_A7_ROOT_SRC] = imx_clk_mux("arm_a7_src", base + 0x8000, 
24, 3, arm_a7_sel, ARRAY_SIZE(arm_a7_sel));
-   clks[IMX7D_ARM_M4_ROOT_SRC] = imx_clk_mux("arm_m4_src", base + 0x8080, 
24, 3, arm_m4_sel, ARRAY_SIZE(arm_m4_sel));
-   clks[IMX7D_ARM_M0_ROOT_SRC] = imx_clk_mux("arm_m0_src", base + 0x8100, 
24, 3, arm_m0_sel, ARRAY_SIZE(arm_m0_sel));
-   clks[IMX7D_MAIN_AXI_ROOT_SRC] = imx_clk_mux("axi_src", base + 0x8800, 
24, 3, axi_sel, ARRAY_SIZE(axi_sel));
-   clks[IMX7D_DISP_AXI_ROOT_SRC] = imx_clk_mux("disp_axi_src", base + 
0x8880, 24, 3, disp_axi_sel, ARRAY_SIZE(disp_axi_sel));
-   clks[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_mux("enet_axi_src", base + 
0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel));
-   clks[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_mux("nand_usdhc_src", 
base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel));
-   clks[IMX7D_AHB_CHANNEL_ROOT_SRC] = imx_clk_mux("ahb_src", base + 
0x9000, 24, 3, ahb_channel_sel, ARRAY_SIZE(ahb_channel_sel));
-   clks[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_mux("dram_phym_src", base + 
0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel));
-   clks[IMX7D_DRAM_ROOT_SRC] = imx_clk_mux("dram_src", base + 0x9880, 24, 
1, dram_sel, ARRAY_SIZE(dram_sel));
-   clks[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_mux("dram_phym_alt_src", 
base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel));
-   clks[IMX7D_DRAM_ALT_ROOT_SRC]  = imx_clk_mux("dram_alt_src", base + 
0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel));
-   clks[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_mux("usb_hsic_src", base + 
0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel));
-   clks[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_mux("pcie_ctrl_src", base + 
0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel));
-   clks[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_mux("pcie_phy_src", base + 
0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel));
-   clks[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_mux("epdc_pixel_src", base + 
0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel));
-   clks[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_mux("lcdif_pixel_src", base 
+ 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel));
-   clks[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_mux("mipi_dsi_src", base + 
0xa380, 24, 3,  mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel));
-   clks[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_mux("mipi_csi_src", base + 
0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel));
-   clks[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_mux("mipi_dphy_src", base + 
0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel));
-   clks[IMX7D_SAI1_ROOT_SRC] = imx_clk_mux("sai1_src", base + 0xa500, 24, 
3, sai1_sel, ARRAY_SIZE(sai1_sel));
-   clks[IMX7D_SAI2_ROOT_SRC] = imx_clk_mux("sai2_src", base + 0xa580, 24, 
3, sai2_sel, ARRAY_SIZE(sai2_sel));
-   clks[IMX7D_SAI3_ROOT_SRC] = imx_clk_mux("sai3_src", base + 0xa600, 24, 
3, sai3_sel, ARRAY_SIZE(sai3_sel));
-   clks[IMX7D_SPDIF_ROOT_SRC] = imx_clk_mux("spdif_src", base + 0xa680, 
24, 3, spdif_sel, ARRAY_SIZE(spdif_sel));
-   clks[IMX7D_ENET1_REF_ROOT_SRC] = imx_clk_mux("enet1_ref_src", base + 
0xa700, 24, 3, enet1_ref_sel, ARRAY_SIZE(enet1_ref_sel));
-   clks[IMX7D_ENET1_TIME_ROOT_SRC] = imx_clk_mux("enet1_time_src", base + 
0xa780, 24, 3, enet1_time_sel, ARRAY_SIZE(enet1_time_sel));
-   clks[IMX7D_ENET2_REF_ROOT_SRC] = imx_clk_mux("enet2_ref_src", base + 
0xa800, 24, 3, enet2_ref_sel, ARRAY_SIZE(enet2_ref_sel));
-   clks[IMX7D_ENET2_TIME_ROOT_SRC] = imx_clk_mux("enet2_time_src", base + 
0xa880, 24, 3, enet2_time_sel, ARRAY_SIZE(enet2_time_sel));
-   clks[IMX7D_ENET_PHY_REF_ROOT_SRC] = imx_clk_mux("enet_phy_ref_src", 
base + 0xa900, 24, 3, enet_phy_ref_sel, ARRAY_SIZE(enet_phy_ref_sel));
-   clks[IMX7D_EIM_ROOT_SRC] = imx_clk_mux("eim_src", base + 0xa980, 24, 3, 
eim_sel, ARRAY_SIZE(eim_sel));
-   clks[IMX7D_NAND_ROOT_SRC] = imx_clk_mux("nand_src", base + 0xaa00, 24, 
3, nand_sel, ARRAY_SIZE(nand_sel));
-   clks[IMX7D_QSPI_ROOT_SRC] = imx_clk_mux("qspi_src", base + 0xaa80, 24, 
3, qspi_sel, ARRAY_SIZE(qspi_sel));

[PATCH V3 7/8] clk: imx7d: using api with flag CLK_OPS_PARENT_ENABLE

2016-06-30 Thread Dong Aisheng 
i.MX7D requires all clocks operations including enable/disable,
rate change and re-parent with its parent clock on.
Changing to the correct APIs to tell clk core such requirement.

Cc: Michael Turquette 
Cc: Stephen Boyd 
Cc: Shawn Guo 
Signed-off-by: Dong Aisheng 
---
 drivers/clk/imx/clk-imx7d.c | 714 ++--
 1 file changed, 357 insertions(+), 357 deletions(-)

diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 522996800d5b..bb5affae0850 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -474,363 +474,363 @@ static void __init imx7d_clocks_init(struct device_node 
*ccm_node)
base = of_iomap(np, 0);
WARN_ON(!base);
 
-   clks[IMX7D_ARM_A7_ROOT_SRC] = imx_clk_mux("arm_a7_src", base + 0x8000, 
24, 3, arm_a7_sel, ARRAY_SIZE(arm_a7_sel));
-   clks[IMX7D_ARM_M4_ROOT_SRC] = imx_clk_mux("arm_m4_src", base + 0x8080, 
24, 3, arm_m4_sel, ARRAY_SIZE(arm_m4_sel));
-   clks[IMX7D_ARM_M0_ROOT_SRC] = imx_clk_mux("arm_m0_src", base + 0x8100, 
24, 3, arm_m0_sel, ARRAY_SIZE(arm_m0_sel));
-   clks[IMX7D_MAIN_AXI_ROOT_SRC] = imx_clk_mux("axi_src", base + 0x8800, 
24, 3, axi_sel, ARRAY_SIZE(axi_sel));
-   clks[IMX7D_DISP_AXI_ROOT_SRC] = imx_clk_mux("disp_axi_src", base + 
0x8880, 24, 3, disp_axi_sel, ARRAY_SIZE(disp_axi_sel));
-   clks[IMX7D_ENET_AXI_ROOT_SRC] = imx_clk_mux("enet_axi_src", base + 
0x8900, 24, 3, enet_axi_sel, ARRAY_SIZE(enet_axi_sel));
-   clks[IMX7D_NAND_USDHC_BUS_ROOT_SRC] = imx_clk_mux("nand_usdhc_src", 
base + 0x8980, 24, 3, nand_usdhc_bus_sel, ARRAY_SIZE(nand_usdhc_bus_sel));
-   clks[IMX7D_AHB_CHANNEL_ROOT_SRC] = imx_clk_mux("ahb_src", base + 
0x9000, 24, 3, ahb_channel_sel, ARRAY_SIZE(ahb_channel_sel));
-   clks[IMX7D_DRAM_PHYM_ROOT_SRC] = imx_clk_mux("dram_phym_src", base + 
0x9800, 24, 1, dram_phym_sel, ARRAY_SIZE(dram_phym_sel));
-   clks[IMX7D_DRAM_ROOT_SRC] = imx_clk_mux("dram_src", base + 0x9880, 24, 
1, dram_sel, ARRAY_SIZE(dram_sel));
-   clks[IMX7D_DRAM_PHYM_ALT_ROOT_SRC] = imx_clk_mux("dram_phym_alt_src", 
base + 0xa000, 24, 3, dram_phym_alt_sel, ARRAY_SIZE(dram_phym_alt_sel));
-   clks[IMX7D_DRAM_ALT_ROOT_SRC]  = imx_clk_mux("dram_alt_src", base + 
0xa080, 24, 3, dram_alt_sel, ARRAY_SIZE(dram_alt_sel));
-   clks[IMX7D_USB_HSIC_ROOT_SRC] = imx_clk_mux("usb_hsic_src", base + 
0xa100, 24, 3, usb_hsic_sel, ARRAY_SIZE(usb_hsic_sel));
-   clks[IMX7D_PCIE_CTRL_ROOT_SRC] = imx_clk_mux("pcie_ctrl_src", base + 
0xa180, 24, 3, pcie_ctrl_sel, ARRAY_SIZE(pcie_ctrl_sel));
-   clks[IMX7D_PCIE_PHY_ROOT_SRC] = imx_clk_mux("pcie_phy_src", base + 
0xa200, 24, 3, pcie_phy_sel, ARRAY_SIZE(pcie_phy_sel));
-   clks[IMX7D_EPDC_PIXEL_ROOT_SRC] = imx_clk_mux("epdc_pixel_src", base + 
0xa280, 24, 3, epdc_pixel_sel, ARRAY_SIZE(epdc_pixel_sel));
-   clks[IMX7D_LCDIF_PIXEL_ROOT_SRC] = imx_clk_mux("lcdif_pixel_src", base 
+ 0xa300, 24, 3, lcdif_pixel_sel, ARRAY_SIZE(lcdif_pixel_sel));
-   clks[IMX7D_MIPI_DSI_ROOT_SRC] = imx_clk_mux("mipi_dsi_src", base + 
0xa380, 24, 3,  mipi_dsi_sel, ARRAY_SIZE(mipi_dsi_sel));
-   clks[IMX7D_MIPI_CSI_ROOT_SRC] = imx_clk_mux("mipi_csi_src", base + 
0xa400, 24, 3, mipi_csi_sel, ARRAY_SIZE(mipi_csi_sel));
-   clks[IMX7D_MIPI_DPHY_ROOT_SRC] = imx_clk_mux("mipi_dphy_src", base + 
0xa480, 24, 3, mipi_dphy_sel, ARRAY_SIZE(mipi_dphy_sel));
-   clks[IMX7D_SAI1_ROOT_SRC] = imx_clk_mux("sai1_src", base + 0xa500, 24, 
3, sai1_sel, ARRAY_SIZE(sai1_sel));
-   clks[IMX7D_SAI2_ROOT_SRC] = imx_clk_mux("sai2_src", base + 0xa580, 24, 
3, sai2_sel, ARRAY_SIZE(sai2_sel));
-   clks[IMX7D_SAI3_ROOT_SRC] = imx_clk_mux("sai3_src", base + 0xa600, 24, 
3, sai3_sel, ARRAY_SIZE(sai3_sel));
-   clks[IMX7D_SPDIF_ROOT_SRC] = imx_clk_mux("spdif_src", base + 0xa680, 
24, 3, spdif_sel, ARRAY_SIZE(spdif_sel));
-   clks[IMX7D_ENET1_REF_ROOT_SRC] = imx_clk_mux("enet1_ref_src", base + 
0xa700, 24, 3, enet1_ref_sel, ARRAY_SIZE(enet1_ref_sel));
-   clks[IMX7D_ENET1_TIME_ROOT_SRC] = imx_clk_mux("enet1_time_src", base + 
0xa780, 24, 3, enet1_time_sel, ARRAY_SIZE(enet1_time_sel));
-   clks[IMX7D_ENET2_REF_ROOT_SRC] = imx_clk_mux("enet2_ref_src", base + 
0xa800, 24, 3, enet2_ref_sel, ARRAY_SIZE(enet2_ref_sel));
-   clks[IMX7D_ENET2_TIME_ROOT_SRC] = imx_clk_mux("enet2_time_src", base + 
0xa880, 24, 3, enet2_time_sel, ARRAY_SIZE(enet2_time_sel));
-   clks[IMX7D_ENET_PHY_REF_ROOT_SRC] = imx_clk_mux("enet_phy_ref_src", 
base + 0xa900, 24, 3, enet_phy_ref_sel, ARRAY_SIZE(enet_phy_ref_sel));
-   clks[IMX7D_EIM_ROOT_SRC] = imx_clk_mux("eim_src", base + 0xa980, 24, 3, 
eim_sel, ARRAY_SIZE(eim_sel));
-   clks[IMX7D_NAND_ROOT_SRC] = imx_clk_mux("nand_src", base + 0xaa00, 24, 
3, nand_sel, ARRAY_SIZE(nand_sel));
-   clks[IMX7D_QSPI_ROOT_SRC] = imx_clk_mux("qspi_src", base + 0xaa80, 24, 
3, qspi_sel, ARRAY_SIZE(qspi_sel));
-   clks[IMX7D_USDHC1_ROOT_SRC] = imx_clk_mux("usdhc1_src", base + 0xab00, 
24, 3,