Re: [PATCH V4 XRT Alveo 03/20] fpga: xrt: xclbin file helper functions
Hi Tom,
On 03/29/2021 10:12 AM, Tom Rix wrote:
On 3/23/21 10:29 PM, Lizhi Hou wrote:
Alveo FPGA firmware and partial reconfigure file are in xclbin format. This
code enumerates and extracts sections from xclbin files. xclbin.h is cross
platform and used across all platforms and OS.
ok
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/xclbin-helper.h | 48 +++
drivers/fpga/xrt/lib/xclbin.c| 369
include/uapi/linux/xrt/xclbin.h | 409 +++
3 files changed, 826 insertions(+)
create mode 100644 drivers/fpga/xrt/include/xclbin-helper.h
create mode 100644 drivers/fpga/xrt/lib/xclbin.c
create mode 100644 include/uapi/linux/xrt/xclbin.h
diff --git a/drivers/fpga/xrt/include/xclbin-helper.h
b/drivers/fpga/xrt/include/xclbin-helper.h
new file mode 100644
index ..382b1de97b0a
--- /dev/null
+++ b/drivers/fpga/xrt/include/xclbin-helper.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ *David Zhang
+ *Sonal Santan
+ */
+
+#ifndef _XCLBIN_HELPER_H_
+#define _XCLBIN_HELPER_H_
ok
+
+#include
+#include
+#include
+
+#define XCLBIN_VERSION2 "xclbin2"
+#define XCLBIN_HWICAP_BITFILE_BUF_SZ 1024
+#define XCLBIN_MAX_SIZE (1024 * 1024 * 1024) /* Assuming xclbin <= 1G, always
*/
ok
+
+enum axlf_section_kind;
+struct axlf;
+
+/**
+ * Bitstream header information as defined by Xilinx tools.
+ * Please note that this struct definition is not owned by the driver.
+ */
+struct xclbin_bit_head_info {
+ u32 header_length; /* Length of header in 32 bit words */
+ u32 bitstream_length; /* Length of bitstream to read in bytes */
+ const unchar *design_name; /* Design name get from bitstream */
+ const unchar *part_name;/* Part name read from bitstream */
+ const unchar *date; /* Date read from bitstream header */
+ const unchar *time; /* Bitstream creation time */
+ u32 magic_length; /* Length of the magic numbers */
+ const unchar *version; /* Version string */
+};
+
ok, bit removed.
+/* caller must free the allocated memory for **data. len could be NULL. */
+int xrt_xclbin_get_section(struct device *dev, const struct axlf *xclbin,
+enum axlf_section_kind kind, void **data,
+uint64_t *len);
need to add comment that user must free data
need to add comment that len is optional
It sounds the comment above the function.
/* caller must free the allocated memory for **data. len could be NULL.
*/
Do you mean I need to add more detail or format the comment in different way?
+int xrt_xclbin_get_metadata(struct device *dev, const struct axlf *xclbin,
char **dtb);
+int xrt_xclbin_parse_bitstream_header(struct device *dev, const unchar *data,
+ u32 size, struct xclbin_bit_head_info
*head_info);
+const char *xrt_clock_type2epname(enum XCLBIN_CLOCK_TYPE type);
ok
+
+#endif /* _XCLBIN_HELPER_H_ */
diff --git a/drivers/fpga/xrt/lib/xclbin.c b/drivers/fpga/xrt/lib/xclbin.c
new file mode 100644
index ..31b363c014a3
--- /dev/null
+++ b/drivers/fpga/xrt/lib/xclbin.c
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Alveo FPGA Driver XCLBIN parser
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors: David Zhang
+ */
+
+#include
+#include
+#include
+#include "xclbin-helper.h"
+#include "metadata.h"
+
+/* Used for parsing bitstream header */
+#define BITSTREAM_EVEN_MAGIC_BYTE0x0f
+#define BITSTREAM_ODD_MAGIC_BYTE 0xf0
ok
+
+static int xrt_xclbin_get_section_hdr(const struct axlf *xclbin,
+ enum axlf_section_kind kind,
+ const struct axlf_section_header **header)
+{
+ const struct axlf_section_header *phead = NULL;
+ u64 xclbin_len;
+ int i;
+
+ *header = NULL;
+ for (i = 0; i < xclbin->header.num_sections; i++) {
+ if (xclbin->sections[i].section_kind == kind) {
+ phead = >sections[i];
+ break;
+ }
+ }
+
+ if (!phead)
+ return -ENOENT;
+
+ xclbin_len = xclbin->header.length;
+ if (xclbin_len > XCLBIN_MAX_SIZE ||
+ phead->section_offset + phead->section_size > xclbin_len)
+ return -EINVAL;
+
+ *header = phead;
+ return 0;
+}
+
+static int xrt_xclbin_section_info(const struct axlf *xclbin,
+enum axlf_section_kind kind,
+u64 *offset, u64 *size)
+{
+ const struct axlf_section_header *mem_header = NULL;
+ int rc;
+
+ rc = xrt_xclbin_get_section_hdr(xclbin, kind, _header);
+ if (rc)
+ return rc;
+
+ *offset = mem_header->section_offset;
+ *size =
Re: [PATCH V4 XRT Alveo 03/20] fpga: xrt: xclbin file helper functions
On 3/23/21 10:29 PM, Lizhi Hou wrote:
> Alveo FPGA firmware and partial reconfigure file are in xclbin format. This
> code enumerates and extracts sections from xclbin files. xclbin.h is cross
> platform and used across all platforms and OS.
ok
>
> Signed-off-by: Sonal Santan
> Signed-off-by: Max Zhen
> Signed-off-by: Lizhi Hou
> ---
> drivers/fpga/xrt/include/xclbin-helper.h | 48 +++
> drivers/fpga/xrt/lib/xclbin.c| 369
> include/uapi/linux/xrt/xclbin.h | 409 +++
> 3 files changed, 826 insertions(+)
> create mode 100644 drivers/fpga/xrt/include/xclbin-helper.h
> create mode 100644 drivers/fpga/xrt/lib/xclbin.c
> create mode 100644 include/uapi/linux/xrt/xclbin.h
>
> diff --git a/drivers/fpga/xrt/include/xclbin-helper.h
> b/drivers/fpga/xrt/include/xclbin-helper.h
> new file mode 100644
> index ..382b1de97b0a
> --- /dev/null
> +++ b/drivers/fpga/xrt/include/xclbin-helper.h
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2020-2021 Xilinx, Inc.
> + *
> + * Authors:
> + *David Zhang
> + *Sonal Santan
> + */
> +
> +#ifndef _XCLBIN_HELPER_H_
> +#define _XCLBIN_HELPER_H_
ok
> +
> +#include
> +#include
> +#include
> +
> +#define XCLBIN_VERSION2 "xclbin2"
> +#define XCLBIN_HWICAP_BITFILE_BUF_SZ 1024
> +#define XCLBIN_MAX_SIZE (1024 * 1024 * 1024) /* Assuming xclbin <= 1G,
> always */
ok
> +
> +enum axlf_section_kind;
> +struct axlf;
> +
> +/**
> + * Bitstream header information as defined by Xilinx tools.
> + * Please note that this struct definition is not owned by the driver.
> + */
> +struct xclbin_bit_head_info {
> + u32 header_length; /* Length of header in 32 bit words */
> + u32 bitstream_length; /* Length of bitstream to read in bytes
> */
> + const unchar *design_name; /* Design name get from bitstream */
> + const unchar *part_name;/* Part name read from bitstream */
> + const unchar *date; /* Date read from bitstream header */
> + const unchar *time; /* Bitstream creation time */
> + u32 magic_length; /* Length of the magic numbers */
> + const unchar *version; /* Version string */
> +};
> +
ok, bit removed.
> +/* caller must free the allocated memory for **data. len could be NULL. */
> +int xrt_xclbin_get_section(struct device *dev, const struct axlf *xclbin,
> +enum axlf_section_kind kind, void **data,
> +uint64_t *len);
need to add comment that user must free data
need to add comment that len is optional
> +int xrt_xclbin_get_metadata(struct device *dev, const struct axlf *xclbin,
> char **dtb);
> +int xrt_xclbin_parse_bitstream_header(struct device *dev, const unchar *data,
> + u32 size, struct xclbin_bit_head_info
> *head_info);
> +const char *xrt_clock_type2epname(enum XCLBIN_CLOCK_TYPE type);
ok
> +
> +#endif /* _XCLBIN_HELPER_H_ */
> diff --git a/drivers/fpga/xrt/lib/xclbin.c b/drivers/fpga/xrt/lib/xclbin.c
> new file mode 100644
> index ..31b363c014a3
> --- /dev/null
> +++ b/drivers/fpga/xrt/lib/xclbin.c
> @@ -0,0 +1,369 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Xilinx Alveo FPGA Driver XCLBIN parser
> + *
> + * Copyright (C) 2020-2021 Xilinx, Inc.
> + *
> + * Authors: David Zhang
> + */
> +
> +#include
> +#include
> +#include
> +#include "xclbin-helper.h"
> +#include "metadata.h"
> +
> +/* Used for parsing bitstream header */
> +#define BITSTREAM_EVEN_MAGIC_BYTE0x0f
> +#define BITSTREAM_ODD_MAGIC_BYTE 0xf0
ok
> +
> +static int xrt_xclbin_get_section_hdr(const struct axlf *xclbin,
> + enum axlf_section_kind kind,
> + const struct axlf_section_header **header)
> +{
> + const struct axlf_section_header *phead = NULL;
> + u64 xclbin_len;
> + int i;
> +
> + *header = NULL;
> + for (i = 0; i < xclbin->header.num_sections; i++) {
> + if (xclbin->sections[i].section_kind == kind) {
> + phead = >sections[i];
> + break;
> + }
> + }
> +
> + if (!phead)
> + return -ENOENT;
> +
> + xclbin_len = xclbin->header.length;
> + if (xclbin_len > XCLBIN_MAX_SIZE ||
> + phead->section_offset + phead->section_size > xclbin_len)
> + return -EINVAL;
> +
> + *header = phead;
> + return 0;
> +}
> +
> +static int xrt_xclbin_section_info(const struct axlf *xclbin,
> +enum axlf_section_kind kind,
> +u64 *offset, u64 *size)
> +{
> + const struct axlf_section_header *mem_header = NULL;
> + int rc;
> +
> + rc = xrt_xclbin_get_section_hdr(xclbin, kind, _header);
> + if (rc)
> + return rc;
> +
> + *offset = mem_header->section_offset;
> + *size =
[PATCH V4 XRT Alveo 03/20] fpga: xrt: xclbin file helper functions
Alveo FPGA firmware and partial reconfigure file are in xclbin format. This
code enumerates and extracts sections from xclbin files. xclbin.h is cross
platform and used across all platforms and OS.
Signed-off-by: Sonal Santan
Signed-off-by: Max Zhen
Signed-off-by: Lizhi Hou
---
drivers/fpga/xrt/include/xclbin-helper.h | 48 +++
drivers/fpga/xrt/lib/xclbin.c| 369
include/uapi/linux/xrt/xclbin.h | 409 +++
3 files changed, 826 insertions(+)
create mode 100644 drivers/fpga/xrt/include/xclbin-helper.h
create mode 100644 drivers/fpga/xrt/lib/xclbin.c
create mode 100644 include/uapi/linux/xrt/xclbin.h
diff --git a/drivers/fpga/xrt/include/xclbin-helper.h
b/drivers/fpga/xrt/include/xclbin-helper.h
new file mode 100644
index ..382b1de97b0a
--- /dev/null
+++ b/drivers/fpga/xrt/include/xclbin-helper.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors:
+ *David Zhang
+ *Sonal Santan
+ */
+
+#ifndef _XCLBIN_HELPER_H_
+#define _XCLBIN_HELPER_H_
+
+#include
+#include
+#include
+
+#define XCLBIN_VERSION2"xclbin2"
+#define XCLBIN_HWICAP_BITFILE_BUF_SZ 1024
+#define XCLBIN_MAX_SIZE (1024 * 1024 * 1024) /* Assuming xclbin <= 1G, always
*/
+
+enum axlf_section_kind;
+struct axlf;
+
+/**
+ * Bitstream header information as defined by Xilinx tools.
+ * Please note that this struct definition is not owned by the driver.
+ */
+struct xclbin_bit_head_info {
+ u32 header_length; /* Length of header in 32 bit words */
+ u32 bitstream_length; /* Length of bitstream to read in bytes
*/
+ const unchar *design_name; /* Design name get from bitstream */
+ const unchar *part_name;/* Part name read from bitstream */
+ const unchar *date; /* Date read from bitstream header */
+ const unchar *time; /* Bitstream creation time */
+ u32 magic_length; /* Length of the magic numbers */
+ const unchar *version; /* Version string */
+};
+
+/* caller must free the allocated memory for **data. len could be NULL. */
+int xrt_xclbin_get_section(struct device *dev, const struct axlf *xclbin,
+ enum axlf_section_kind kind, void **data,
+ uint64_t *len);
+int xrt_xclbin_get_metadata(struct device *dev, const struct axlf *xclbin,
char **dtb);
+int xrt_xclbin_parse_bitstream_header(struct device *dev, const unchar *data,
+ u32 size, struct xclbin_bit_head_info
*head_info);
+const char *xrt_clock_type2epname(enum XCLBIN_CLOCK_TYPE type);
+
+#endif /* _XCLBIN_HELPER_H_ */
diff --git a/drivers/fpga/xrt/lib/xclbin.c b/drivers/fpga/xrt/lib/xclbin.c
new file mode 100644
index ..31b363c014a3
--- /dev/null
+++ b/drivers/fpga/xrt/lib/xclbin.c
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Alveo FPGA Driver XCLBIN parser
+ *
+ * Copyright (C) 2020-2021 Xilinx, Inc.
+ *
+ * Authors: David Zhang
+ */
+
+#include
+#include
+#include
+#include "xclbin-helper.h"
+#include "metadata.h"
+
+/* Used for parsing bitstream header */
+#define BITSTREAM_EVEN_MAGIC_BYTE 0x0f
+#define BITSTREAM_ODD_MAGIC_BYTE 0xf0
+
+static int xrt_xclbin_get_section_hdr(const struct axlf *xclbin,
+ enum axlf_section_kind kind,
+ const struct axlf_section_header **header)
+{
+ const struct axlf_section_header *phead = NULL;
+ u64 xclbin_len;
+ int i;
+
+ *header = NULL;
+ for (i = 0; i < xclbin->header.num_sections; i++) {
+ if (xclbin->sections[i].section_kind == kind) {
+ phead = >sections[i];
+ break;
+ }
+ }
+
+ if (!phead)
+ return -ENOENT;
+
+ xclbin_len = xclbin->header.length;
+ if (xclbin_len > XCLBIN_MAX_SIZE ||
+ phead->section_offset + phead->section_size > xclbin_len)
+ return -EINVAL;
+
+ *header = phead;
+ return 0;
+}
+
+static int xrt_xclbin_section_info(const struct axlf *xclbin,
+ enum axlf_section_kind kind,
+ u64 *offset, u64 *size)
+{
+ const struct axlf_section_header *mem_header = NULL;
+ int rc;
+
+ rc = xrt_xclbin_get_section_hdr(xclbin, kind, _header);
+ if (rc)
+ return rc;
+
+ *offset = mem_header->section_offset;
+ *size = mem_header->section_size;
+
+ return 0;
+}
+
+/* caller must free the allocated memory for **data */
+int xrt_xclbin_get_section(struct device *dev,
+ const struct axlf *buf,
+ enum axlf_section_kind kind,
+ void **data, u64 *len)
+{
+ const struct axlf *xclbin =
