Re: [PATCH V5 4/4] gpio: tegra: Add support for gpio debounce

[Linus Walleij]

On Mon, Apr 25, 2016 at 12:38 PM, Laxman Dewangan  wrote:

> NVIDIA's Tegra210 support the HW debounce in the GPIO controller
> for all its GPIO pins.
>
> Add support for setting debounce timing by implementing the
> set_debounce callback of gpiochip.
>
> Signed-off-by: Laxman Dewangan 
> Reviewed-by: Stephen Warren 

Patch applied, also added Alex' review tag.

Yours,
Linus Walleij

Re: [PATCH V5 4/4] gpio: tegra: Add support for gpio debounce

[Linus Walleij]

On Mon, Apr 25, 2016 at 12:38 PM, Laxman Dewangan  wrote:

> NVIDIA's Tegra210 support the HW debounce in the GPIO controller
> for all its GPIO pins.
>
> Add support for setting debounce timing by implementing the
> set_debounce callback of gpiochip.
>
> Signed-off-by: Laxman Dewangan 
> Reviewed-by: Stephen Warren 

Patch applied, also added Alex' review tag.

Yours,
Linus Walleij

Re: [PATCH V5 4/4] gpio: tegra: Add support for gpio debounce

[Alexandre Courbot]

On Mon, Apr 25, 2016 at 7:38 PM, Laxman Dewangan  wrote:
> NVIDIA's Tegra210 support the HW debounce in the GPIO controller
> for all its GPIO pins.
>
> Add support for setting debounce timing by implementing the
> set_debounce callback of gpiochip.
>
> Signed-off-by: Laxman Dewangan 
> Reviewed-by: Stephen Warren 

Reviewed-by: Alexandre Courbot 

Re: [PATCH V5 4/4] gpio: tegra: Add support for gpio debounce

[Alexandre Courbot]

On Mon, Apr 25, 2016 at 7:38 PM, Laxman Dewangan  wrote:
> NVIDIA's Tegra210 support the HW debounce in the GPIO controller
> for all its GPIO pins.
>
> Add support for setting debounce timing by implementing the
> set_debounce callback of gpiochip.
>
> Signed-off-by: Laxman Dewangan 
> Reviewed-by: Stephen Warren 

Reviewed-by: Alexandre Courbot 

[PATCH V5 4/4] gpio: tegra: Add support for gpio debounce

[Laxman Dewangan]

NVIDIA's Tegra210 support the HW debounce in the GPIO controller
for all its GPIO pins.

Add support for setting debounce timing by implementing the
set_debounce callback of gpiochip.

Signed-off-by: Laxman Dewangan 
Reviewed-by: Stephen Warren 

---
Changes from V1:
- Write debounce count before enable.
- Make sure the debounce count do not have any boot residuals.

Changes from V2:
- Only access register for debounce when SoC support debounce.

Changes from V3:
- Add locking mechanism in debounce count register update.
- Move DBC register from prev patch to here.

Changes from V3:
- Rewrite the set_debounce to have bank_info as local pointer for easy to read.
- Collected RB from Stephen.
---
 drivers/gpio/gpio-tegra.c | 69 ++-
 1 file changed, 68 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 653825d..b3ddd92 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -46,10 +46,13 @@
 #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
 #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
 #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
+#define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
+
 
 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
 #define GPIO_MSK_OE(t, x)  (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
+#define GPIO_MSK_DBC_EN(t, x)  (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
 #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
@@ -67,6 +70,7 @@ struct tegra_gpio_bank {
int bank;
int irq;
spinlock_t lvl_lock[4];
+   spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
 #ifdef CONFIG_PM_SLEEP
u32 cnf[4];
u32 out[4];
@@ -74,11 +78,14 @@ struct tegra_gpio_bank {
u32 int_enb[4];
u32 int_lvl[4];
u32 wake_enb[4];
+   u32 dbc_enb[4];
 #endif
+   u32 dbc_cnt[4];
struct tegra_gpio_info *tgi;
 };
 
 struct tegra_gpio_soc_config {
+   bool debounce_supported;
u32 bank_stride;
u32 upper_offset;
 };
@@ -184,6 +191,39 @@ static int tegra_gpio_direction_output(struct gpio_chip 
*chip, unsigned offset,
return 0;
 }
 
+static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
+  unsigned int debounce)
+{
+   struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
+   struct tegra_gpio_bank *bank = >bank_info[GPIO_BANK(offset)];
+   unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
+   unsigned long flags;
+   int port;
+
+   if (!debounce_ms) {
+   tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
+ offset, 0);
+   return 0;
+   }
+
+   debounce_ms = min(debounce_ms, 255U);
+   port = GPIO_PORT(offset);
+
+   /* There is only one debounce count register per port and hence
+* set the maximum of current and requested debounce time.
+*/
+   spin_lock_irqsave(>dbc_lock[port], flags);
+   if (bank->dbc_cnt[port] < debounce_ms) {
+   tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
+   bank->dbc_cnt[port] = debounce_ms;
+   }
+   spin_unlock_irqrestore(>dbc_lock[port], flags);
+
+   tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
+
+   return 0;
+}
+
 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 {
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
@@ -350,6 +390,14 @@ static int tegra_gpio_resume(struct device *dev)
unsigned int gpio = (b<<5) | (p<<3);
tegra_gpio_writel(tgi, bank->cnf[p],
  GPIO_CNF(tgi, gpio));
+
+   if (tgi->soc->debounce_supported) {
+   tegra_gpio_writel(tgi, bank->dbc_cnt[p],
+ GPIO_DBC_CNT(tgi, gpio));
+   tegra_gpio_writel(tgi, bank->dbc_enb[p],
+ GPIO_MSK_DBC_EN(tgi, gpio));
+   }
+
tegra_gpio_writel(tgi, bank->out[p],
  GPIO_OUT(tgi, gpio));
tegra_gpio_writel(tgi, bank->oe[p],
@@ -385,6 +433,13 @@ static int tegra_gpio_suspend(struct device *dev)
GPIO_OUT(tgi, gpio));
bank->oe[p] = tegra_gpio_readl(tgi,
   

[PATCH V5 4/4] gpio: tegra: Add support for gpio debounce

[Laxman Dewangan]

NVIDIA's Tegra210 support the HW debounce in the GPIO controller
for all its GPIO pins.

Add support for setting debounce timing by implementing the
set_debounce callback of gpiochip.

Signed-off-by: Laxman Dewangan 
Reviewed-by: Stephen Warren 

---
Changes from V1:
- Write debounce count before enable.
- Make sure the debounce count do not have any boot residuals.

Changes from V2:
- Only access register for debounce when SoC support debounce.

Changes from V3:
- Add locking mechanism in debounce count register update.
- Move DBC register from prev patch to here.

Changes from V3:
- Rewrite the set_debounce to have bank_info as local pointer for easy to read.
- Collected RB from Stephen.
---
 drivers/gpio/gpio-tegra.c | 69 ++-
 1 file changed, 68 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 653825d..b3ddd92 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -46,10 +46,13 @@
 #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
 #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
 #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
+#define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
+
 
 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
 #define GPIO_MSK_OE(t, x)  (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
+#define GPIO_MSK_DBC_EN(t, x)  (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
 #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
@@ -67,6 +70,7 @@ struct tegra_gpio_bank {
int bank;
int irq;
spinlock_t lvl_lock[4];
+   spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
 #ifdef CONFIG_PM_SLEEP
u32 cnf[4];
u32 out[4];
@@ -74,11 +78,14 @@ struct tegra_gpio_bank {
u32 int_enb[4];
u32 int_lvl[4];
u32 wake_enb[4];
+   u32 dbc_enb[4];
 #endif
+   u32 dbc_cnt[4];
struct tegra_gpio_info *tgi;
 };
 
 struct tegra_gpio_soc_config {
+   bool debounce_supported;
u32 bank_stride;
u32 upper_offset;
 };
@@ -184,6 +191,39 @@ static int tegra_gpio_direction_output(struct gpio_chip 
*chip, unsigned offset,
return 0;
 }
 
+static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
+  unsigned int debounce)
+{
+   struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
+   struct tegra_gpio_bank *bank = >bank_info[GPIO_BANK(offset)];
+   unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
+   unsigned long flags;
+   int port;
+
+   if (!debounce_ms) {
+   tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
+ offset, 0);
+   return 0;
+   }
+
+   debounce_ms = min(debounce_ms, 255U);
+   port = GPIO_PORT(offset);
+
+   /* There is only one debounce count register per port and hence
+* set the maximum of current and requested debounce time.
+*/
+   spin_lock_irqsave(>dbc_lock[port], flags);
+   if (bank->dbc_cnt[port] < debounce_ms) {
+   tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
+   bank->dbc_cnt[port] = debounce_ms;
+   }
+   spin_unlock_irqrestore(>dbc_lock[port], flags);
+
+   tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
+
+   return 0;
+}
+
 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 {
struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
@@ -350,6 +390,14 @@ static int tegra_gpio_resume(struct device *dev)
unsigned int gpio = (b<<5) | (p<<3);
tegra_gpio_writel(tgi, bank->cnf[p],
  GPIO_CNF(tgi, gpio));
+
+   if (tgi->soc->debounce_supported) {
+   tegra_gpio_writel(tgi, bank->dbc_cnt[p],
+ GPIO_DBC_CNT(tgi, gpio));
+   tegra_gpio_writel(tgi, bank->dbc_enb[p],
+ GPIO_MSK_DBC_EN(tgi, gpio));
+   }
+
tegra_gpio_writel(tgi, bank->out[p],
  GPIO_OUT(tgi, gpio));
tegra_gpio_writel(tgi, bank->oe[p],
@@ -385,6 +433,13 @@ static int tegra_gpio_suspend(struct device *dev)
GPIO_OUT(tgi, gpio));
bank->oe[p] = tegra_gpio_readl(tgi,
   GPIO_OE(tgi, gpio));
+