Use direct register operations instead of a table of register
information to lower the stack usage.
Signed-off-by: Steen Hegelund
Reported-by: kernel test robot
---
drivers/phy/microchip/sparx5_serdes.c | 1869 +
1 file changed, 951 insertions(+), 918 deletions(-)
diff --git a/drivers/phy/microchip/sparx5_serdes.c
b/drivers/phy/microchip/sparx5_serdes.c
index 06bcf0c166cf..338a4220b45f 100644
--- a/drivers/phy/microchip/sparx5_serdes.c
+++ b/drivers/phy/microchip/sparx5_serdes.c
@@ -343,12 +343,6 @@ struct sparx5_sd10g28_params {
u8 fx_100;
};
-struct sparx5_serdes_regval {
- u32 value;
- u32 mask;
- void __iomem *addr;
-};
-
static struct sparx5_sd25g28_media_preset media_presets_25g[] = {
{ /* ETH_MEDIA_DEFAULT */
.cfg_en_adv = 0,
@@ -945,431 +939,411 @@ static void sparx5_sd25g28_reset(void __iomem *regs[],
}
}
-static int sparx5_sd25g28_apply_params(struct device *dev,
- void __iomem *regs[],
- struct sparx5_sd25g28_params *params,
- u32 sd_index)
+static int sparx5_sd25g28_apply_params(struct sparx5_serdes_macro *macro,
+ struct sparx5_sd25g28_params *params)
{
- struct sparx5_serdes_regval item[] = {
- {
- SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(1),
- SD_LANE_25G_SD_LANE_CFG_MACRO_RST,
- sdx5_addr(regs, SD_LANE_25G_SD_LANE_CFG(sd_index))
- },
- {
- SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xFF),
- SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,
- sdx5_addr(regs, SD25G_LANE_CMU_FF(sd_index))
- },
- {
- SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET
- (params->r_d_width_ctrl_from_hwt) |
-
SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(params->r_reg_manual),
- SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT |
- SD25G_LANE_CMU_1A_R_REG_MANUAL,
- sdx5_addr(regs, SD25G_LANE_CMU_1A(sd_index))
- },
- {
- SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET
- (params->cfg_common_reserve_7_0),
- SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0,
- sdx5_addr(regs, SD25G_LANE_CMU_31(sd_index))
- },
- {
-
SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(params->cfg_en_dummy),
- SD25G_LANE_CMU_09_CFG_EN_DUMMY,
- sdx5_addr(regs, SD25G_LANE_CMU_09(sd_index))
- },
- {
-
SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(params->cfg_pll_reserve_3_0),
- SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0,
- sdx5_addr(regs, SD25G_LANE_CMU_13(sd_index))
- },
- {
-
SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(params->l0_cfg_txcal_en),
- SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN,
- sdx5_addr(regs, SD25G_LANE_CMU_40(sd_index))
- },
- {
- SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET
- (params->l0_cfg_tx_reserve_15_8),
- SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8,
- sdx5_addr(regs, SD25G_LANE_CMU_46(sd_index))
- },
- {
-
SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(params->l0_cfg_tx_reserve_7_0),
- SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0,
- sdx5_addr(regs, SD25G_LANE_CMU_45(sd_index))
- },
- {
- SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(0),
- SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN,
- sdx5_addr(regs, SD25G_LANE_CMU_0B(sd_index))
- },
- {
- SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(1),
- SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN,
- sdx5_addr(regs, SD25G_LANE_CMU_0B(sd_index))
- },
- {
- SD25G_LANE_CMU_19_R_CK_RESETB_SET(0),
- SD25G_LANE_CMU_19_R_CK_RESETB,
- sdx5_addr(regs, SD25G_LANE_CMU_19(sd_index))
- },
- {
- SD25G_LANE_CMU_19_R_CK_RESETB_SET(1),
- SD25G_LANE_CMU_19_R_CK_RESETB,
- sdx5_addr(regs, SD25G_LANE_CMU_19(sd_index))
- },
- {
- SD25G_LANE_CMU_18_R_PLL_RSTN_SET(0),
-