Re: [PATCH v0 3/4] drivers: edac: Add cache erp driver for Last Level Cache Controller (LLCC)
On Mon, Jul 30, 2018 at 02:38:01PM -0700, vnkgu...@codeaurora.org wrote: > Do you mean the Signed-off-by lines above? That's because > Channagoud is the one who is the original author of this driver, > and I'm the one who did the incremental changes (changes in llcc) > and uploading it upstream. > That's why the Signed-off is like that. > Which way do you think it should be? Then you need to figure out between you two who the author should be because we have single authorship. When you do, commit it in git with git commit --amend --author=... so that that is reflected properly. For expressing stuff like co-authorship we have Co-Developed-by: All explained in submitting-patches.rst. -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. --
Re: [PATCH v0 3/4] drivers: edac: Add cache erp driver for Last Level Cache Controller (LLCC)
On 2018-07-28 20:49, Borislav Petkov wrote: On Wed, Jul 25, 2018 at 10:44:56AM -0700, Venkata Narendra Kumar Gutta wrote: Add cache error reporting driver for single and double bit errors on Last Level Cache Controller (LLCC) cache. This driver takes care of dumping registers and add config options to enable and disable panic when these errors happen. Signed-off-by: Channagoud Kadabi Signed-off-by: Venkata Narendra Kumar Gutta This SOB chain doesn't make any sense - see Documentation/process/submitting-patches.rst Do you mean the Signed-off-by lines above? That's because Channagoud is the one who is the original author of this driver, and I'm the one who did the incremental changes (changes in llcc) and uploading it upstream. That's why the Signed-off is like that. Which way do you think it should be? --- drivers/edac/Kconfig | 21 ++ drivers/edac/Makefile | 1 + drivers/edac/qcom_llcc_edac.c | 520 ++ 3 files changed, 542 insertions(+) create mode 100644 drivers/edac/qcom_llcc_edac.c Needs MAINTAINERS entry so that you get all the bug reports. I'll update it. diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 57304b2..68518ad 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -460,4 +460,25 @@ config EDAC_TI Support for error detection and correction on the TI SoCs. +config EDAC_QCOM_LLCC +depends on QCOM_LLCC +tristate "QCOM EDAC Controller for LLCC Cache" No edac driver per functional unit pls - see how altera_edac.c does it, for example. IOW, this driver - if it cannot share/reuse any of the existing edac drivers, it should be called qcom_edac and contain all the Qualcomm-specific RAS features there. Ok, I'll refactor it. +help + Support for error detection and correction on the + QCOM LLCC cache. Report errors caught by LLCC ECC + mechanism. + + For debugging issues having to do with stability and overall system + health, you should probably say 'Y' here. + +config EDAC_QCOM_LLCC_PANIC_ON_UE +depends on EDAC_QCOM_LLCC +bool "Panic on uncorrectable errors - qcom llcc" +help + Forcibly cause a kernel panic if an uncorrectable error (UE) is + detected. This can reduce debugging times on hardware which may be + operating at voltages or frequencies outside normal specification. + + For production builds, you should probably say 'N' here. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 02b43a7..28aff28 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o obj-$(CONFIG_EDAC_SYNOPSYS)+= synopsys_edac.o obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o obj-$(CONFIG_EDAC_TI) += ti_edac.o +obj-$(CONFIG_EDAC_QCOM_LLCC) += qcom_llcc_edac.o diff --git a/drivers/edac/qcom_llcc_edac.c b/drivers/edac/qcom_llcc_edac.c new file mode 100644 index 000..7a678b5 --- /dev/null +++ b/drivers/edac/qcom_llcc_edac.c @@ -0,0 +1,520 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "edac_mc.h" +#include "edac_device.h" + +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE +#define LLCC_ERP_PANIC_ON_UE 1 +#else +#define LLCC_ERP_PANIC_ON_UE 0 +#endif + +#define EDAC_LLCC "qcom_llcc" + +#define TRP_SYN_REG_CNT6 + +#define DRP_SYN_REG_CNT8 + +#define LLCC_COMMON_STATUS00x0003000C +#define LLCC_LB_CNT_MASK GENMASK(31, 28) +#define LLCC_LB_CNT_SHIFT 28 + +/* single & Double Bit syndrome register offsets */ +#define TRP_ECC_SB_ERR_SYN00x0002304C +#define TRP_ECC_DB_ERR_SYN00x00020370 +#define DRP_ECC_SB_ERR_SYN00x0004204C +#define DRP_ECC_DB_ERR_SYN00x00042070 + +/* Error register offsets */ +#define TRP_ECC_ERROR_STATUS1 0x00020348 +#define TRP_ECC_ERROR_STATUS0 0x00020344 +#define DRP_ECC_ERROR_STATUS1 0x00042048 +#define DRP_ECC_ERROR_STATUS0 0x00042044 + +/* TRP, DRP interrupt register offsets */ +#define DRP_INTERRUPT_STATUS 0x00041000 +#define TRP_INTERRUPT_0_STATUS 0x00020480 +#define DRP_INTERRUPT_CLEAR0x00041008 +#define DRP_ECC_ERROR_CNTR_CLEAR 0x00040004 +#define TRP_INTERRUPT_0_CLEAR 0x00020484 +#define TRP_ECC_ERROR_CNTR_CLEAR 0x00020440 + +/* Mask and shift macros */ +#define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0) Align all those to the same vertical column. Sure, I'll update it in the next patch set. +#define ECC_DB_ERR_WAYS_MASK GENMASK(31, 16) +#define ECC_DB_ERR_WAYS_SHIFT BIT(4) + +#define ECC_SB_ERR_COUNT_MASK GENMASK
Re: [PATCH v0 3/4] drivers: edac: Add cache erp driver for Last Level Cache Controller (LLCC)
On Wed, Jul 25, 2018 at 10:44:56AM -0700, Venkata Narendra Kumar Gutta wrote: > Add cache error reporting driver for single and double bit errors on > Last Level Cache Controller (LLCC) cache. This driver takes care of > dumping registers and add config options to enable and disable panic > when these errors happen. > > Signed-off-by: Channagoud Kadabi > Signed-off-by: Venkata Narendra Kumar Gutta This SOB chain doesn't make any sense - see Documentation/process/submitting-patches.rst > --- > drivers/edac/Kconfig | 21 ++ > drivers/edac/Makefile | 1 + > drivers/edac/qcom_llcc_edac.c | 520 > ++ > 3 files changed, 542 insertions(+) > create mode 100644 drivers/edac/qcom_llcc_edac.c Needs MAINTAINERS entry so that you get all the bug reports. > diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig > index 57304b2..68518ad 100644 > --- a/drivers/edac/Kconfig > +++ b/drivers/edac/Kconfig > @@ -460,4 +460,25 @@ config EDAC_TI > Support for error detection and correction on the >TI SoCs. > > +config EDAC_QCOM_LLCC > +depends on QCOM_LLCC > +tristate "QCOM EDAC Controller for LLCC Cache" No edac driver per functional unit pls - see how altera_edac.c does it, for example. IOW, this driver - if it cannot share/reuse any of the existing edac drivers, it should be called qcom_edac and contain all the Qualcomm-specific RAS features there. > +help > + Support for error detection and correction on the > + QCOM LLCC cache. Report errors caught by LLCC ECC > + mechanism. > + > + For debugging issues having to do with stability and overall system > + health, you should probably say 'Y' here. > + > +config EDAC_QCOM_LLCC_PANIC_ON_UE > +depends on EDAC_QCOM_LLCC > +bool "Panic on uncorrectable errors - qcom llcc" > +help > + Forcibly cause a kernel panic if an uncorrectable error (UE) is > + detected. This can reduce debugging times on hardware which may be > + operating at voltages or frequencies outside normal specification. > + > + For production builds, you should probably say 'N' here. > + > endif # EDAC > diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile > index 02b43a7..28aff28 100644 > --- a/drivers/edac/Makefile > +++ b/drivers/edac/Makefile > @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o > obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o > obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o > obj-$(CONFIG_EDAC_TI)+= ti_edac.o > +obj-$(CONFIG_EDAC_QCOM_LLCC) += qcom_llcc_edac.o > diff --git a/drivers/edac/qcom_llcc_edac.c b/drivers/edac/qcom_llcc_edac.c > new file mode 100644 > index 000..7a678b5 > --- /dev/null > +++ b/drivers/edac/qcom_llcc_edac.c > @@ -0,0 +1,520 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2018, The Linux Foundation. All rights reserved. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "edac_mc.h" > +#include "edac_device.h" > + > +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE > +#define LLCC_ERP_PANIC_ON_UE 1 > +#else > +#define LLCC_ERP_PANIC_ON_UE 0 > +#endif > + > +#define EDAC_LLCC"qcom_llcc" > + > +#define TRP_SYN_REG_CNT 6 > + > +#define DRP_SYN_REG_CNT 8 > + > +#define LLCC_COMMON_STATUS0 0x0003000C > +#define LLCC_LB_CNT_MASK GENMASK(31, 28) > +#define LLCC_LB_CNT_SHIFT28 > + > +/* single & Double Bit syndrome register offsets */ > +#define TRP_ECC_SB_ERR_SYN0 0x0002304C > +#define TRP_ECC_DB_ERR_SYN0 0x00020370 > +#define DRP_ECC_SB_ERR_SYN0 0x0004204C > +#define DRP_ECC_DB_ERR_SYN0 0x00042070 > + > +/* Error register offsets */ > +#define TRP_ECC_ERROR_STATUS10x00020348 > +#define TRP_ECC_ERROR_STATUS00x00020344 > +#define DRP_ECC_ERROR_STATUS10x00042048 > +#define DRP_ECC_ERROR_STATUS00x00042044 > + > +/* TRP, DRP interrupt register offsets */ > +#define DRP_INTERRUPT_STATUS 0x00041000 > +#define TRP_INTERRUPT_0_STATUS 0x00020480 > +#define DRP_INTERRUPT_CLEAR 0x00041008 > +#define DRP_ECC_ERROR_CNTR_CLEAR 0x00040004 > +#define TRP_INTERRUPT_0_CLEAR0x00020484 > +#define TRP_ECC_ERROR_CNTR_CLEAR 0x00020440 > + > +/* Mask and shift macros */ > +#define ECC_DB_ERR_COUNT_MASKGENMASK(4, 0) Align all those to the same vertical column. > +#define ECC_DB_ERR_WAYS_MASK GENMASK(31, 16) > +#define ECC_DB_ERR_WAYS_SHIFTBIT(4) > + > +#define ECC_SB_ERR_COUNT_MASKGENMASK(23, 16) > +#define ECC_SB_ERR_COUNT_SHIFT BIT(4) > +#define ECC_SB_ERR_WAYS_MASK GENMASK(15, 0) > + > +#define SB_ECC_ERROR BIT(0) > +#define DB_ECC_ERROR BIT(1) > + > +#defi
[PATCH v0 3/4] drivers: edac: Add cache erp driver for Last Level Cache Controller (LLCC)
Add cache error reporting driver for single and double bit errors on
Last Level Cache Controller (LLCC) cache. This driver takes care of
dumping registers and add config options to enable and disable panic
when these errors happen.
Signed-off-by: Channagoud Kadabi
Signed-off-by: Venkata Narendra Kumar Gutta
---
drivers/edac/Kconfig | 21 ++
drivers/edac/Makefile | 1 +
drivers/edac/qcom_llcc_edac.c | 520 ++
3 files changed, 542 insertions(+)
create mode 100644 drivers/edac/qcom_llcc_edac.c
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 57304b2..68518ad 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -460,4 +460,25 @@ config EDAC_TI
Support for error detection and correction on the
TI SoCs.
+config EDAC_QCOM_LLCC
+depends on QCOM_LLCC
+tristate "QCOM EDAC Controller for LLCC Cache"
+help
+ Support for error detection and correction on the
+ QCOM LLCC cache. Report errors caught by LLCC ECC
+ mechanism.
+
+ For debugging issues having to do with stability and overall system
+ health, you should probably say 'Y' here.
+
+config EDAC_QCOM_LLCC_PANIC_ON_UE
+depends on EDAC_QCOM_LLCC
+bool "Panic on uncorrectable errors - qcom llcc"
+help
+ Forcibly cause a kernel panic if an uncorrectable error (UE) is
+ detected. This can reduce debugging times on hardware which may be
+ operating at voltages or frequencies outside normal specification.
+
+ For production builds, you should probably say 'N' here.
+
endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 02b43a7..28aff28 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o
obj-$(CONFIG_EDAC_SYNOPSYS)+= synopsys_edac.o
obj-$(CONFIG_EDAC_XGENE) += xgene_edac.o
obj-$(CONFIG_EDAC_TI) += ti_edac.o
+obj-$(CONFIG_EDAC_QCOM_LLCC) += qcom_llcc_edac.o
diff --git a/drivers/edac/qcom_llcc_edac.c b/drivers/edac/qcom_llcc_edac.c
new file mode 100644
index 000..7a678b5
--- /dev/null
+++ b/drivers/edac/qcom_llcc_edac.c
@@ -0,0 +1,520 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "edac_mc.h"
+#include "edac_device.h"
+
+#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
+#define LLCC_ERP_PANIC_ON_UE 1
+#else
+#define LLCC_ERP_PANIC_ON_UE 0
+#endif
+
+#define EDAC_LLCC "qcom_llcc"
+
+#define TRP_SYN_REG_CNT6
+
+#define DRP_SYN_REG_CNT8
+
+#define LLCC_COMMON_STATUS00x0003000C
+#define LLCC_LB_CNT_MASK GENMASK(31, 28)
+#define LLCC_LB_CNT_SHIFT 28
+
+/* single & Double Bit syndrome register offsets */
+#define TRP_ECC_SB_ERR_SYN00x0002304C
+#define TRP_ECC_DB_ERR_SYN00x00020370
+#define DRP_ECC_SB_ERR_SYN00x0004204C
+#define DRP_ECC_DB_ERR_SYN00x00042070
+
+/* Error register offsets */
+#define TRP_ECC_ERROR_STATUS1 0x00020348
+#define TRP_ECC_ERROR_STATUS0 0x00020344
+#define DRP_ECC_ERROR_STATUS1 0x00042048
+#define DRP_ECC_ERROR_STATUS0 0x00042044
+
+/* TRP, DRP interrupt register offsets */
+#define DRP_INTERRUPT_STATUS 0x00041000
+#define TRP_INTERRUPT_0_STATUS 0x00020480
+#define DRP_INTERRUPT_CLEAR0x00041008
+#define DRP_ECC_ERROR_CNTR_CLEAR 0x00040004
+#define TRP_INTERRUPT_0_CLEAR 0x00020484
+#define TRP_ECC_ERROR_CNTR_CLEAR 0x00020440
+
+/* Mask and shift macros */
+#define ECC_DB_ERR_COUNT_MASK GENMASK(4, 0)
+#define ECC_DB_ERR_WAYS_MASK GENMASK(31, 16)
+#define ECC_DB_ERR_WAYS_SHIFT BIT(4)
+
+#define ECC_SB_ERR_COUNT_MASK GENMASK(23, 16)
+#define ECC_SB_ERR_COUNT_SHIFT BIT(4)
+#define ECC_SB_ERR_WAYS_MASK GENMASK(15, 0)
+
+#define SB_ECC_ERROR BIT(0)
+#define DB_ECC_ERROR BIT(1)
+
+#define DRP_TRP_INT_CLEAR GENMASK(1, 0)
+#define DRP_TRP_CNT_CLEAR GENMASK(1, 0)
+
+/* Config registers offsets*/
+#define DRP_ECC_ERROR_CFG 0x0004
+
+/* TRP, DRP interrupt register offsets */
+#define CMN_INTERRUPT_0_ENABLE 0x0003001C
+#define CMN_INTERRUPT_2_ENABLE 0x0003003C
+#define TRP_INTERRUPT_0_ENABLE 0x00020488
+#define DRP_INTERRUPT_ENABLE0x0004100C
+
+#define SB_ERROR_THRESHOLD 0x1
+#define SB_ERROR_THRESHOLD_SHIFT24
+#define SB_DB_TRP_INTERRUPT_ENABLE 0x3
+#define TRP0_INTERRUPT_ENABLE 0x1
+#define DRP0_INTERRUPT_ENABLE BIT(6)
+#define SB_DB_DRP_INTERRUPT_ENABLE 0x3
+
+
+enum {
+ LLCC_DRAM_CE = 0,
+ LLCC_DRAM_UE,
+ LLCC_TRAM_CE,
+ LLCC_TRAM_UE,
+};
+
+struct errors_edac {
+
