Re: [PATCH v1 2/2] pinctrl: rockchip: only enable gpio clock when it setting
Am Montag, 3. August 2015, 13:21:27 schrieb Doug Anderson:
> hl
>
> On Sun, Aug 2, 2015 at 8:56 PM, huang lin wrote:
> > gpio can keep state even the clock disable, for save power
> > consumption, only enable gpio clock when it setting
> >
> > Signed-off-by: Heiko Stuebner
> > Signed-off-by: huang lin
> >
> > Signed-off-by: huang lin
>
> Your "Signed-off-by"s are a little wonky here... Can you fix up?
>
> > ---
> >
> > drivers/pinctrl/pinctrl-rockchip.c | 60
> > ++ 1 file changed, 54 insertions(+),
> > 6 deletions(-)
> >
> > diff --git a/drivers/pinctrl/pinctrl-rockchip.c
> > b/drivers/pinctrl/pinctrl-rockchip.c index cc2843a..445829f 100644
> > --- a/drivers/pinctrl/pinctrl-rockchip.c
> > +++ b/drivers/pinctrl/pinctrl-rockchip.c
> > @@ -945,17 +945,20 @@ static int _rockchip_pmx_gpio_set_direction(struct
> > gpio_chip *chip,>
> > if (ret < 0)
> >
> > return ret;
> >
> > + clk_enable(bank->clk);
> >
> > spin_lock_irqsave(>slock, flags);
> >
> > - data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
> > + data = readl(bank->reg_base + GPIO_SWPORT_DDR);
>
> I am a little curious why you need to change the readl_relaxed() to a
> read(). Are you trying to ensure that the clock was on before the
> read happened? If so, I think this won't help. I see:
>
> #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
>
> ...so that means that the iormb() is _after_ the readl.
>
> ...but I would believe that the clk_enable() call itself would be
> guaranteeing that the clock was enabled in time. ...and if not then
> grabbing the spinlock is another barrier, right? I think you do this
> in a few places...
>
> Other than that this patch looks good to me
I think that was my fault ... looking at stuff before figuring out that we're
actually loosing the pd_pmu clock, and then forgetting to take this out again,
before getting it to hl.
In retospect it also seems silly to have changed them in the first place ;-) .
So yes, they should be changed back to their original.
Heiko
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Re: [PATCH v1 2/2] pinctrl: rockchip: only enable gpio clock when it setting
hl
On Sun, Aug 2, 2015 at 8:56 PM, huang lin wrote:
> gpio can keep state even the clock disable, for save power
> consumption, only enable gpio clock when it setting
>
> Signed-off-by: Heiko Stuebner
> Signed-off-by: huang lin
>
> Signed-off-by: huang lin
Your "Signed-off-by"s are a little wonky here... Can you fix up?
> ---
> drivers/pinctrl/pinctrl-rockchip.c | 60
> ++
> 1 file changed, 54 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-rockchip.c
> b/drivers/pinctrl/pinctrl-rockchip.c
> index cc2843a..445829f 100644
> --- a/drivers/pinctrl/pinctrl-rockchip.c
> +++ b/drivers/pinctrl/pinctrl-rockchip.c
> @@ -945,17 +945,20 @@ static int _rockchip_pmx_gpio_set_direction(struct
> gpio_chip *chip,
> if (ret < 0)
> return ret;
>
> + clk_enable(bank->clk);
> spin_lock_irqsave(>slock, flags);
>
> - data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
> + data = readl(bank->reg_base + GPIO_SWPORT_DDR);
I am a little curious why you need to change the readl_relaxed() to a
read(). Are you trying to ensure that the clock was on before the
read happened? If so, I think this won't help. I see:
#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
...so that means that the iormb() is _after_ the readl.
...but I would believe that the clk_enable() call itself would be
guaranteeing that the clock was enabled in time. ...and if not then
grabbing the spinlock is another barrier, right? I think you do this
in a few places...
Other than that this patch looks good to me
-Doug
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Re: [PATCH v1 2/2] pinctrl: rockchip: only enable gpio clock when it setting
Am Montag, 3. August 2015, 13:21:27 schrieb Doug Anderson:
hl
On Sun, Aug 2, 2015 at 8:56 PM, huang lin h...@rock-chips.com wrote:
gpio can keep state even the clock disable, for save power
consumption, only enable gpio clock when it setting
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: huang lin h...@rock-chips.com
Signed-off-by: huang lin h...@rock-chips.com
Your Signed-off-bys are a little wonky here... Can you fix up?
---
drivers/pinctrl/pinctrl-rockchip.c | 60
++ 1 file changed, 54 insertions(+),
6 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c
b/drivers/pinctrl/pinctrl-rockchip.c index cc2843a..445829f 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -945,17 +945,20 @@ static int _rockchip_pmx_gpio_set_direction(struct
gpio_chip *chip,
if (ret 0)
return ret;
+ clk_enable(bank-clk);
spin_lock_irqsave(bank-slock, flags);
- data = readl_relaxed(bank-reg_base + GPIO_SWPORT_DDR);
+ data = readl(bank-reg_base + GPIO_SWPORT_DDR);
I am a little curious why you need to change the readl_relaxed() to a
read(). Are you trying to ensure that the clock was on before the
read happened? If so, I think this won't help. I see:
#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
...so that means that the iormb() is _after_ the readl.
...but I would believe that the clk_enable() call itself would be
guaranteeing that the clock was enabled in time. ...and if not then
grabbing the spinlock is another barrier, right? I think you do this
in a few places...
Other than that this patch looks good to me
I think that was my fault ... looking at stuff before figuring out that we're
actually loosing the pd_pmu clock, and then forgetting to take this out again,
before getting it to hl.
In retospect it also seems silly to have changed them in the first place ;-) .
So yes, they should be changed back to their original.
Heiko
--
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v1 2/2] pinctrl: rockchip: only enable gpio clock when it setting
hl
On Sun, Aug 2, 2015 at 8:56 PM, huang lin h...@rock-chips.com wrote:
gpio can keep state even the clock disable, for save power
consumption, only enable gpio clock when it setting
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: huang lin h...@rock-chips.com
Signed-off-by: huang lin h...@rock-chips.com
Your Signed-off-bys are a little wonky here... Can you fix up?
---
drivers/pinctrl/pinctrl-rockchip.c | 60
++
1 file changed, 54 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c
b/drivers/pinctrl/pinctrl-rockchip.c
index cc2843a..445829f 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -945,17 +945,20 @@ static int _rockchip_pmx_gpio_set_direction(struct
gpio_chip *chip,
if (ret 0)
return ret;
+ clk_enable(bank-clk);
spin_lock_irqsave(bank-slock, flags);
- data = readl_relaxed(bank-reg_base + GPIO_SWPORT_DDR);
+ data = readl(bank-reg_base + GPIO_SWPORT_DDR);
I am a little curious why you need to change the readl_relaxed() to a
read(). Are you trying to ensure that the clock was on before the
read happened? If so, I think this won't help. I see:
#define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
...so that means that the iormb() is _after_ the readl.
...but I would believe that the clk_enable() call itself would be
guaranteeing that the clock was enabled in time. ...and if not then
grabbing the spinlock is another barrier, right? I think you do this
in a few places...
Other than that this patch looks good to me
-Doug
--
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the body of a message to majord...@vger.kernel.org
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Please read the FAQ at http://www.tux.org/lkml/
[PATCH v1 2/2] pinctrl: rockchip: only enable gpio clock when it setting
gpio can keep state even the clock disable, for save power
consumption, only enable gpio clock when it setting
Signed-off-by: Heiko Stuebner
Signed-off-by: huang lin
Signed-off-by: huang lin
---
drivers/pinctrl/pinctrl-rockchip.c | 60 ++
1 file changed, 54 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c
b/drivers/pinctrl/pinctrl-rockchip.c
index cc2843a..445829f 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -945,17 +945,20 @@ static int _rockchip_pmx_gpio_set_direction(struct
gpio_chip *chip,
if (ret < 0)
return ret;
+ clk_enable(bank->clk);
spin_lock_irqsave(>slock, flags);
- data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
+ data = readl(bank->reg_base + GPIO_SWPORT_DDR);
/* set bit to 1 for output, 0 for input */
if (!input)
data |= BIT(pin);
else
data &= ~BIT(pin);
+
writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
spin_unlock_irqrestore(>slock, flags);
+ clk_disable(bank->clk);
return 0;
}
@@ -1389,6 +1392,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc,
unsigned offset, int value)
unsigned long flags;
u32 data;
+ clk_enable(bank->clk);
spin_lock_irqsave(>slock, flags);
data = readl(reg);
@@ -1398,6 +1402,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc,
unsigned offset, int value)
writel(data, reg);
spin_unlock_irqrestore(>slock, flags);
+ clk_disable(bank->clk);
}
/*
@@ -1409,7 +1414,9 @@ static int rockchip_gpio_get(struct gpio_chip *gc,
unsigned offset)
struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
u32 data;
+ clk_enable(bank->clk);
data = readl(bank->reg_base + GPIO_EXT_PORT);
+ clk_disable(bank->clk);
data >>= offset;
data &= 1;
return data;
@@ -1546,9 +1553,10 @@ static int rockchip_irq_set_type(struct irq_data *d,
unsigned int type)
if (ret < 0)
return ret;
+ clk_enable(bank->clk);
spin_lock_irqsave(>slock, flags);
- data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
+ data = readl(bank->reg_base + GPIO_SWPORT_DDR);
data &= ~mask;
writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
@@ -1603,6 +1611,7 @@ static int rockchip_irq_set_type(struct irq_data *d,
unsigned int type)
default:
irq_gc_unlock(gc);
spin_unlock_irqrestore(>slock, flags);
+ clk_disable(bank->clk);
return -EINVAL;
}
@@ -1611,6 +1620,7 @@ static int rockchip_irq_set_type(struct irq_data *d,
unsigned int type)
irq_gc_unlock(gc);
spin_unlock_irqrestore(>slock, flags);
+ clk_disable(bank->clk);
return 0;
}
@@ -1620,8 +1630,10 @@ static void rockchip_irq_suspend(struct irq_data *d)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc->private;
+ clk_enable(bank->clk);
bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
+ clk_disable(bank->clk);
}
static void rockchip_irq_resume(struct irq_data *d)
@@ -1629,7 +1641,27 @@ static void rockchip_irq_resume(struct irq_data *d)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc->private;
+ clk_enable(bank->clk);
irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
+ clk_disable(bank->clk);
+}
+
+static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct rockchip_pin_bank *bank = gc->private;
+
+ clk_enable(bank->clk);
+ irq_gc_mask_clr_bit(d);
+}
+
+void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct rockchip_pin_bank *bank = gc->private;
+
+ irq_gc_mask_set_bit(d);
+ clk_disable(bank->clk);
}
static int rockchip_interrupts_register(struct platform_device *pdev,
@@ -1640,7 +1672,7 @@ static int rockchip_interrupts_register(struct
platform_device *pdev,
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct irq_chip_generic *gc;
int ret;
- int i;
+ int i, j;
for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
if (!bank->valid) {
@@ -1649,11 +1681,19 @@ static int rockchip_interrupts_register(struct
platform_device *pdev,
continue;
}
+ ret = clk_enable(bank->clk);
+ if (ret) {
+ dev_err(>dev, "failed to enable clock for bank
%s\n",
+
[PATCH v1 2/2] pinctrl: rockchip: only enable gpio clock when it setting
gpio can keep state even the clock disable, for save power
consumption, only enable gpio clock when it setting
Signed-off-by: Heiko Stuebner he...@sntech.de
Signed-off-by: huang lin h...@rock-chips.com
Signed-off-by: huang lin h...@rock-chips.com
---
drivers/pinctrl/pinctrl-rockchip.c | 60 ++
1 file changed, 54 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c
b/drivers/pinctrl/pinctrl-rockchip.c
index cc2843a..445829f 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -945,17 +945,20 @@ static int _rockchip_pmx_gpio_set_direction(struct
gpio_chip *chip,
if (ret 0)
return ret;
+ clk_enable(bank-clk);
spin_lock_irqsave(bank-slock, flags);
- data = readl_relaxed(bank-reg_base + GPIO_SWPORT_DDR);
+ data = readl(bank-reg_base + GPIO_SWPORT_DDR);
/* set bit to 1 for output, 0 for input */
if (!input)
data |= BIT(pin);
else
data = ~BIT(pin);
+
writel_relaxed(data, bank-reg_base + GPIO_SWPORT_DDR);
spin_unlock_irqrestore(bank-slock, flags);
+ clk_disable(bank-clk);
return 0;
}
@@ -1389,6 +1392,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc,
unsigned offset, int value)
unsigned long flags;
u32 data;
+ clk_enable(bank-clk);
spin_lock_irqsave(bank-slock, flags);
data = readl(reg);
@@ -1398,6 +1402,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc,
unsigned offset, int value)
writel(data, reg);
spin_unlock_irqrestore(bank-slock, flags);
+ clk_disable(bank-clk);
}
/*
@@ -1409,7 +1414,9 @@ static int rockchip_gpio_get(struct gpio_chip *gc,
unsigned offset)
struct rockchip_pin_bank *bank = gc_to_pin_bank(gc);
u32 data;
+ clk_enable(bank-clk);
data = readl(bank-reg_base + GPIO_EXT_PORT);
+ clk_disable(bank-clk);
data = offset;
data = 1;
return data;
@@ -1546,9 +1553,10 @@ static int rockchip_irq_set_type(struct irq_data *d,
unsigned int type)
if (ret 0)
return ret;
+ clk_enable(bank-clk);
spin_lock_irqsave(bank-slock, flags);
- data = readl_relaxed(bank-reg_base + GPIO_SWPORT_DDR);
+ data = readl(bank-reg_base + GPIO_SWPORT_DDR);
data = ~mask;
writel_relaxed(data, bank-reg_base + GPIO_SWPORT_DDR);
@@ -1603,6 +1611,7 @@ static int rockchip_irq_set_type(struct irq_data *d,
unsigned int type)
default:
irq_gc_unlock(gc);
spin_unlock_irqrestore(bank-slock, flags);
+ clk_disable(bank-clk);
return -EINVAL;
}
@@ -1611,6 +1620,7 @@ static int rockchip_irq_set_type(struct irq_data *d,
unsigned int type)
irq_gc_unlock(gc);
spin_unlock_irqrestore(bank-slock, flags);
+ clk_disable(bank-clk);
return 0;
}
@@ -1620,8 +1630,10 @@ static void rockchip_irq_suspend(struct irq_data *d)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc-private;
+ clk_enable(bank-clk);
bank-saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
irq_reg_writel(gc, ~gc-wake_active, GPIO_INTMASK);
+ clk_disable(bank-clk);
}
static void rockchip_irq_resume(struct irq_data *d)
@@ -1629,7 +1641,27 @@ static void rockchip_irq_resume(struct irq_data *d)
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct rockchip_pin_bank *bank = gc-private;
+ clk_enable(bank-clk);
irq_reg_writel(gc, bank-saved_masks, GPIO_INTMASK);
+ clk_disable(bank-clk);
+}
+
+static void rockchip_irq_gc_mask_clr_bit(struct irq_data *d)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct rockchip_pin_bank *bank = gc-private;
+
+ clk_enable(bank-clk);
+ irq_gc_mask_clr_bit(d);
+}
+
+void rockchip_irq_gc_mask_set_bit(struct irq_data *d)
+{
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct rockchip_pin_bank *bank = gc-private;
+
+ irq_gc_mask_set_bit(d);
+ clk_disable(bank-clk);
}
static int rockchip_interrupts_register(struct platform_device *pdev,
@@ -1640,7 +1672,7 @@ static int rockchip_interrupts_register(struct
platform_device *pdev,
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct irq_chip_generic *gc;
int ret;
- int i;
+ int i, j;
for (i = 0; i ctrl-nr_banks; ++i, ++bank) {
if (!bank-valid) {
@@ -1649,11 +1681,19 @@ static int rockchip_interrupts_register(struct
platform_device *pdev,
continue;
}
+ ret = clk_enable(bank-clk);
+ if (ret) {
+ dev_err(pdev-dev, failed to enable clock for bank
