Re: [PATCH v1 21/24] drivers: thermal: tsens: Add generic support for TSENS v1 IP
On Thu, Feb 07, 2019 at 04:19:39PM +0530, Amit Kucheria wrote:
> qcs404 has a single TSENS IP block with 10 sensors. It uses version 1.4
> of the TSENS IP, functionality for which is encapsulated inside the
> qcom,tsens-v1 compatible.
>
> Signed-off-by: Amit Kucheria
> ---
> drivers/thermal/qcom/Makefile | 4 +-
> drivers/thermal/qcom/tsens-v1.c | 229
> drivers/thermal/qcom/tsens.c| 3 +
> drivers/thermal/qcom/tsens.h| 3 +
> 4 files changed, 238 insertions(+), 1 deletion(-)
> create mode 100644 drivers/thermal/qcom/tsens-v1.c
>
> diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile
> index 7fa3cadce760..fc6fe50cdde4 100644
> --- a/drivers/thermal/qcom/Makefile
> +++ b/drivers/thermal/qcom/Makefile
> @@ -1,3 +1,5 @@
> obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o
> -qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o
> tsens-8960.o tsens-v2.o
> +
> +qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o \
> +tsens-8960.o tsens-v2.o tsens-v1.o
> obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o
> diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c
> new file mode 100644
> index ..417e2c2de1a1
> --- /dev/null
> +++ b/drivers/thermal/qcom/tsens-v1.c
> @@ -0,0 +1,229 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019, Linaro Limited
> + */
> +
> +#include
> +#include
> +#include
> +#include "tsens.h"
> +
> +/* - SROT -- */
> +#define SROT_HW_VER_OFF 0x
> +#define SROT_CTRL_OFF0x0004
> +
> +/* - TM -- */
> +#define TM_INT_EN_OFF0x
> +#define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF0x0004
> +#define TM_Sn_STATUS_OFF 0x0044
> +#define TM_TRDY_OFF 0x0084
> +
> +/* eeprom layout data for qcs404/405 (v1) */
> +#define BASE0_MASK 0x07f8
> +#define BASE1_MASK 0x0007f800
> +#define BASE0_SHIFT 3
> +#define BASE1_SHIFT 11
> +
> +#define S0_P1_MASK 0x003f
> +#define S1_P1_MASK 0x0003f000
> +#define S2_P1_MASK 0x3f00
> +#define S3_P1_MASK 0x03f0
> +#define S4_P1_MASK 0x003f
> +#define S5_P1_MASK 0x003f
> +#define S6_P1_MASK 0x0003f000
> +#define S7_P1_MASK 0x3f00
> +#define S8_P1_MASK 0x03f0
> +#define S9_P1_MASK 0x003f
> +
> +#define S0_P2_MASK 0x0fc0
> +#define S1_P2_MASK 0x00fc
> +#define S2_P2_MASK_1_0 0xc000
> +#define S2_P2_MASK_5_2 0x000f
> +#define S3_P2_MASK 0xfc00
> +#define S4_P2_MASK 0x0fc0
> +#define S5_P2_MASK 0x0fc0
> +#define S6_P2_MASK 0x00fc
> +#define S7_P2_MASK_1_0 0xc000
> +#define S7_P2_MASK_5_2 0x000f
> +#define S8_P2_MASK 0xfc00
> +#define S9_P2_MASK 0x0fc0
> +
> +#define S0_P1_SHIFT 0
> +#define S0_P2_SHIFT 6
> +#define S1_P1_SHIFT 12
> +#define S1_P2_SHIFT 18
> +#define S2_P1_SHIFT 24
> +#define S2_P2_SHIFT_1_0 30
> +
> +#define S2_P2_SHIFT_5_2 0
> +#define S3_P1_SHIFT 4
> +#define S3_P2_SHIFT 10
> +#define S4_P1_SHIFT 16
> +#define S4_P2_SHIFT 22
> +
> +#define S5_P1_SHIFT 0
> +#define S5_P2_SHIFT 6
> +#define S6_P1_SHIFT 12
> +#define S6_P2_SHIFT 18
> +#define S7_P1_SHIFT 24
> +#define S7_P2_SHIFT_1_0 30
> +
> +#define S7_P2_SHIFT_5_2 0
> +#define S8_P1_SHIFT 4
> +#define S8_P2_SHIFT 10
> +#define S9_P1_SHIFT 16
> +#define S9_P2_SHIFT 22
> +
> +#define CAL_SEL_MASK 7
Why not using the macros on bits.h?
> +#define CAL_SEL_SHIFT0
> +
> +static int calibrate_v1(struct tsens_priv *priv)
> +{
> + u32 base0 = 0, base1 = 0;
> + u32 p1[10], p2[10];
> + u32 mode = 0, lsb = 0, msb = 0;
> + u32 *qfprom_cdata;
> + int i;
> +
> + qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
> + if (IS_ERR(qfprom_cdata))
> + return PTR_ERR(qfprom_cdata);
> +
> + mode = (qfprom_cdata[4] & CAL_SEL_MASK) >> CAL_SEL_SHIFT;
> + dev_dbg(priv->dev, "calibration mode is %d\n", mode);
> +
> + switch (mode) {
> + case TWO_PT_CALIB:
> + base1 = (qfprom_cdata[4] & BASE1_MASK) >> BASE1_SHIFT;
> + p2[0] = (qfprom_cdata[0] & S0_P2_MASK) >> S0_P2_SHIFT;
> + p2[1] = (qfprom_cdata[0] & S1_P2_MASK) >> S1_P2_SHIFT;
> + /* This value is split over two registers, 2 bits and 4 bits */
> + lsb = (qfprom_cdata[0] & S2_P2_MASK_1_0) >> S2_P2_SHIFT_1_0;
> + msb = (qfprom_cdata[1] & S2_P2_MASK_5_2) >> S2_P2_SHIFT_5_2;
> + p2[2] = msb << 2 | lsb;
> + p2[3] = (qfprom_cdata[1] & S3_P2_MASK) >> S3_P2_SHIFT;
> + p2[4] = (qfprom_cdata[1] & S4_P2_MASK) >> S4_P2_SHIFT;
> + p2[5] = (qfprom_cdata[2] & S5_P2_MASK) >> S5_P2_SHIFT;
> + p2[6] = (qfprom_cdata[2] & S6_P2_MASK) >> S6_P2_SHIFT;
> + /* This value is split over two
[PATCH v1 21/24] drivers: thermal: tsens: Add generic support for TSENS v1 IP
qcs404 has a single TSENS IP block with 10 sensors. It uses version 1.4
of the TSENS IP, functionality for which is encapsulated inside the
qcom,tsens-v1 compatible.
Signed-off-by: Amit Kucheria
---
drivers/thermal/qcom/Makefile | 4 +-
drivers/thermal/qcom/tsens-v1.c | 229
drivers/thermal/qcom/tsens.c| 3 +
drivers/thermal/qcom/tsens.h| 3 +
4 files changed, 238 insertions(+), 1 deletion(-)
create mode 100644 drivers/thermal/qcom/tsens-v1.c
diff --git a/drivers/thermal/qcom/Makefile b/drivers/thermal/qcom/Makefile
index 7fa3cadce760..fc6fe50cdde4 100644
--- a/drivers/thermal/qcom/Makefile
+++ b/drivers/thermal/qcom/Makefile
@@ -1,3 +1,5 @@
obj-$(CONFIG_QCOM_TSENS) += qcom_tsens.o
-qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o
tsens-8960.o tsens-v2.o
+
+qcom_tsens-y += tsens.o tsens-common.o tsens-v0_1.o \
+ tsens-8960.o tsens-v2.o tsens-v1.o
obj-$(CONFIG_QCOM_SPMI_TEMP_ALARM) += qcom-spmi-temp-alarm.o
diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c
new file mode 100644
index ..417e2c2de1a1
--- /dev/null
+++ b/drivers/thermal/qcom/tsens-v1.c
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019, Linaro Limited
+ */
+
+#include
+#include
+#include
+#include "tsens.h"
+
+/* - SROT -- */
+#define SROT_HW_VER_OFF0x
+#define SROT_CTRL_OFF 0x0004
+
+/* - TM -- */
+#define TM_INT_EN_OFF 0x
+#define TM_Sn_UPPER_LOWER_STATUS_CTRL_OFF 0x0004
+#define TM_Sn_STATUS_OFF 0x0044
+#define TM_TRDY_OFF0x0084
+
+/* eeprom layout data for qcs404/405 (v1) */
+#define BASE0_MASK 0x07f8
+#define BASE1_MASK 0x0007f800
+#define BASE0_SHIFT3
+#define BASE1_SHIFT11
+
+#define S0_P1_MASK 0x003f
+#define S1_P1_MASK 0x0003f000
+#define S2_P1_MASK 0x3f00
+#define S3_P1_MASK 0x03f0
+#define S4_P1_MASK 0x003f
+#define S5_P1_MASK 0x003f
+#define S6_P1_MASK 0x0003f000
+#define S7_P1_MASK 0x3f00
+#define S8_P1_MASK 0x03f0
+#define S9_P1_MASK 0x003f
+
+#define S0_P2_MASK 0x0fc0
+#define S1_P2_MASK 0x00fc
+#define S2_P2_MASK_1_0 0xc000
+#define S2_P2_MASK_5_2 0x000f
+#define S3_P2_MASK 0xfc00
+#define S4_P2_MASK 0x0fc0
+#define S5_P2_MASK 0x0fc0
+#define S6_P2_MASK 0x00fc
+#define S7_P2_MASK_1_0 0xc000
+#define S7_P2_MASK_5_2 0x000f
+#define S8_P2_MASK 0xfc00
+#define S9_P2_MASK 0x0fc0
+
+#define S0_P1_SHIFT0
+#define S0_P2_SHIFT6
+#define S1_P1_SHIFT12
+#define S1_P2_SHIFT18
+#define S2_P1_SHIFT24
+#define S2_P2_SHIFT_1_030
+
+#define S2_P2_SHIFT_5_20
+#define S3_P1_SHIFT4
+#define S3_P2_SHIFT10
+#define S4_P1_SHIFT16
+#define S4_P2_SHIFT22
+
+#define S5_P1_SHIFT0
+#define S5_P2_SHIFT6
+#define S6_P1_SHIFT12
+#define S6_P2_SHIFT18
+#define S7_P1_SHIFT24
+#define S7_P2_SHIFT_1_030
+
+#define S7_P2_SHIFT_5_20
+#define S8_P1_SHIFT4
+#define S8_P2_SHIFT10
+#define S9_P1_SHIFT16
+#define S9_P2_SHIFT22
+
+#define CAL_SEL_MASK 7
+#define CAL_SEL_SHIFT 0
+
+static int calibrate_v1(struct tsens_priv *priv)
+{
+ u32 base0 = 0, base1 = 0;
+ u32 p1[10], p2[10];
+ u32 mode = 0, lsb = 0, msb = 0;
+ u32 *qfprom_cdata;
+ int i;
+
+ qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib");
+ if (IS_ERR(qfprom_cdata))
+ return PTR_ERR(qfprom_cdata);
+
+ mode = (qfprom_cdata[4] & CAL_SEL_MASK) >> CAL_SEL_SHIFT;
+ dev_dbg(priv->dev, "calibration mode is %d\n", mode);
+
+ switch (mode) {
+ case TWO_PT_CALIB:
+ base1 = (qfprom_cdata[4] & BASE1_MASK) >> BASE1_SHIFT;
+ p2[0] = (qfprom_cdata[0] & S0_P2_MASK) >> S0_P2_SHIFT;
+ p2[1] = (qfprom_cdata[0] & S1_P2_MASK) >> S1_P2_SHIFT;
+ /* This value is split over two registers, 2 bits and 4 bits */
+ lsb = (qfprom_cdata[0] & S2_P2_MASK_1_0) >> S2_P2_SHIFT_1_0;
+ msb = (qfprom_cdata[1] & S2_P2_MASK_5_2) >> S2_P2_SHIFT_5_2;
+ p2[2] = msb << 2 | lsb;
+ p2[3] = (qfprom_cdata[1] & S3_P2_MASK) >> S3_P2_SHIFT;
+ p2[4] = (qfprom_cdata[1] & S4_P2_MASK) >> S4_P2_SHIFT;
+ p2[5] = (qfprom_cdata[2] & S5_P2_MASK) >> S5_P2_SHIFT;
+ p2[6] = (qfprom_cdata[2] & S6_P2_MASK) >> S6_P2_SHIFT;
+ /* This value is split over two registers, 2 bits and 4 bits */
+ lsb = (qfprom_cdata[2] & S7_P2_MASK_1_0) >> S7_P2_SHIFT_1_0;
+ msb = (qfprom_cdata[3] & S7_P2_MASK_5_2) >> S7_P2_SHIFT_5_2;
+ p2[7] = msb << 2 | lsb;
+ p2[8] = (qfprom_cdata[3]
