[PATCH v1 3/6] ASoC: mediatek: update MT2701 AFE documentation to adapt mfd device

2018-01-03 Thread Ryder Lee 
As the new MFD parent is in place, modify MT2701 AFE documentation to
adapt it. Also add three core clocks in example.

Signed-off-by: Ryder Lee 
---
 .../devicetree/bindings/sound/mt2701-afe-pcm.txt   | 171 +++--
 1 file changed, 93 insertions(+), 78 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt 
b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
index 0450baa..12f147b 100644
--- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
+++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
@@ -2,15 +2,17 @@ Mediatek AFE PCM controller for mt2701
 
 Required properties:
 - compatible = "mediatek,mt2701-audio";
-- reg: register location and size
 - interrupts: should contain AFE and ASYS interrupts
 - interrupt-names: should be "afe" and "asys"
 - power-domains: should define the power domain
 - clocks: Must contain an entry for each entry in clock-names
   See ../clocks/clock-bindings.txt for details
 - clock-names: should have these clock names:
+   "infra_sys_audio_clk",
"top_audio_mux1_sel",
"top_audio_mux2_sel",
+   "top_audio_a1sys_hp",
+   "top_audio_a2sys_hp",
"i2s0_src_sel",
"i2s1_src_sel",
"i2s2_src_sel",
@@ -45,85 +47,98 @@ Required properties:
 - assigned-clocks-parents: parent of input clocks of assigned clocks.
 - assigned-clock-rates: list of clock frequencies of assigned clocks.
 
+Must be a subnode of MediaTek audsys device tree node.
+See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
+
 Example:
 
-   afe: mt2701-afe-pcm@1122 {
-   compatible = "mediatek,mt2701-audio";
-   reg = <0 0x1122 0 0x2000>,
- <0 0x112A 0 0x2>;
-   interrupts = ,
-;
-   interrupt-names = "afe", "asys";
-   power-domains = < MT2701_POWER_DOMAIN_IFR_MSC>;
-   clocks = < CLK_TOP_AUD_MUX1_SEL>,
-< CLK_TOP_AUD_MUX2_SEL>,
-< CLK_TOP_AUD_K1_SRC_SEL>,
-< CLK_TOP_AUD_K2_SRC_SEL>,
-< CLK_TOP_AUD_K3_SRC_SEL>,
-< CLK_TOP_AUD_K4_SRC_SEL>,
-< CLK_TOP_AUD_K1_SRC_DIV>,
-< CLK_TOP_AUD_K2_SRC_DIV>,
-< CLK_TOP_AUD_K3_SRC_DIV>,
-< CLK_TOP_AUD_K4_SRC_DIV>,
-< CLK_TOP_AUD_I2S1_MCLK>,
-< CLK_TOP_AUD_I2S2_MCLK>,
-< CLK_TOP_AUD_I2S3_MCLK>,
-< CLK_TOP_AUD_I2S4_MCLK>,
-< CLK_AUD_I2SO1>,
-< CLK_AUD_I2SO2>,
-< CLK_AUD_I2SO3>,
-< CLK_AUD_I2SO4>,
-< CLK_AUD_I2SIN1>,
-< CLK_AUD_I2SIN2>,
-< CLK_AUD_I2SIN3>,
-< CLK_AUD_I2SIN4>,
-< CLK_AUD_ASRCO1>,
-< CLK_AUD_ASRCO2>,
-< CLK_AUD_ASRCO3>,
-< CLK_AUD_ASRCO4>,
-< CLK_AUD_AFE>,
-< CLK_AUD_AFE_CONN>,
-< CLK_AUD_A1SYS>,
-< CLK_AUD_A2SYS>,
-< CLK_AUD_AFE_MRGIF>;
+   audsys: audio-subsystem@1122 {
+   compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
+   ...
+
+   afe: audio-controller {
+   compatible = "mediatek,mt2701-audio";
+   interrupts =  ,
+ ;
+   interrupt-names = "afe", "asys";
+   power-domains = < MT2701_POWER_DOMAIN_IFR_MSC>;
+
+   clocks = < CLK_INFRA_AUDIO>,
+< CLK_TOP_AUD_MUX1_SEL>,
+< CLK_TOP_AUD_MUX2_SEL>,
+< CLK_TOP_AUD_48K_TIMING>,
+< CLK_TOP_AUD_44K_TIMING>,
+< CLK_TOP_AUD_K1_SRC_SEL>,
+< CLK_TOP_AUD_K2_SRC_SEL>,
+< CLK_TOP_AUD_K3_SRC_SEL>,
+< CLK_TOP_AUD_K4_SRC_SEL>,
+< CLK_TOP_AUD_K1_SRC_DIV>,
+< CLK_TOP_AUD_K2_SRC_DIV>,
+< CLK_TOP_AUD_K3_SRC_DIV>,
+< CLK_TOP_AUD_K4_SRC_DIV>,
+< CLK_TOP_AUD_I2S1_MCLK>,
+< CLK_TOP_AUD_I2S2_MCLK>,
+< CLK_TOP_AUD_I2S3_MCLK>,
+< CLK_TOP_AUD_I2S4_MCLK>,
+

[PATCH v1 3/6] ASoC: mediatek: update MT2701 AFE documentation to adapt mfd device

2018-01-03 Thread Ryder Lee 
As the new MFD parent is in place, modify MT2701 AFE documentation to
adapt it. Also add three core clocks in example.

Signed-off-by: Ryder Lee 
---
 .../devicetree/bindings/sound/mt2701-afe-pcm.txt   | 171 +++--
 1 file changed, 93 insertions(+), 78 deletions(-)

diff --git a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt 
b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
index 0450baa..12f147b 100644
--- a/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
+++ b/Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
@@ -2,15 +2,17 @@ Mediatek AFE PCM controller for mt2701
 
 Required properties:
 - compatible = "mediatek,mt2701-audio";
-- reg: register location and size
 - interrupts: should contain AFE and ASYS interrupts
 - interrupt-names: should be "afe" and "asys"
 - power-domains: should define the power domain
 - clocks: Must contain an entry for each entry in clock-names
   See ../clocks/clock-bindings.txt for details
 - clock-names: should have these clock names:
+   "infra_sys_audio_clk",
"top_audio_mux1_sel",
"top_audio_mux2_sel",
+   "top_audio_a1sys_hp",
+   "top_audio_a2sys_hp",
"i2s0_src_sel",
"i2s1_src_sel",
"i2s2_src_sel",
@@ -45,85 +47,98 @@ Required properties:
 - assigned-clocks-parents: parent of input clocks of assigned clocks.
 - assigned-clock-rates: list of clock frequencies of assigned clocks.
 
+Must be a subnode of MediaTek audsys device tree node.
+See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
+
 Example:
 
-   afe: mt2701-afe-pcm@1122 {
-   compatible = "mediatek,mt2701-audio";
-   reg = <0 0x1122 0 0x2000>,
- <0 0x112A 0 0x2>;
-   interrupts = ,
-;
-   interrupt-names = "afe", "asys";
-   power-domains = < MT2701_POWER_DOMAIN_IFR_MSC>;
-   clocks = < CLK_TOP_AUD_MUX1_SEL>,
-< CLK_TOP_AUD_MUX2_SEL>,
-< CLK_TOP_AUD_K1_SRC_SEL>,
-< CLK_TOP_AUD_K2_SRC_SEL>,
-< CLK_TOP_AUD_K3_SRC_SEL>,
-< CLK_TOP_AUD_K4_SRC_SEL>,
-< CLK_TOP_AUD_K1_SRC_DIV>,
-< CLK_TOP_AUD_K2_SRC_DIV>,
-< CLK_TOP_AUD_K3_SRC_DIV>,
-< CLK_TOP_AUD_K4_SRC_DIV>,
-< CLK_TOP_AUD_I2S1_MCLK>,
-< CLK_TOP_AUD_I2S2_MCLK>,
-< CLK_TOP_AUD_I2S3_MCLK>,
-< CLK_TOP_AUD_I2S4_MCLK>,
-< CLK_AUD_I2SO1>,
-< CLK_AUD_I2SO2>,
-< CLK_AUD_I2SO3>,
-< CLK_AUD_I2SO4>,
-< CLK_AUD_I2SIN1>,
-< CLK_AUD_I2SIN2>,
-< CLK_AUD_I2SIN3>,
-< CLK_AUD_I2SIN4>,
-< CLK_AUD_ASRCO1>,
-< CLK_AUD_ASRCO2>,
-< CLK_AUD_ASRCO3>,
-< CLK_AUD_ASRCO4>,
-< CLK_AUD_AFE>,
-< CLK_AUD_AFE_CONN>,
-< CLK_AUD_A1SYS>,
-< CLK_AUD_A2SYS>,
-< CLK_AUD_AFE_MRGIF>;
+   audsys: audio-subsystem@1122 {
+   compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
+   ...
+
+   afe: audio-controller {
+   compatible = "mediatek,mt2701-audio";
+   interrupts =  ,
+ ;
+   interrupt-names = "afe", "asys";
+   power-domains = < MT2701_POWER_DOMAIN_IFR_MSC>;
+
+   clocks = < CLK_INFRA_AUDIO>,
+< CLK_TOP_AUD_MUX1_SEL>,
+< CLK_TOP_AUD_MUX2_SEL>,
+< CLK_TOP_AUD_48K_TIMING>,
+< CLK_TOP_AUD_44K_TIMING>,
+< CLK_TOP_AUD_K1_SRC_SEL>,
+< CLK_TOP_AUD_K2_SRC_SEL>,
+< CLK_TOP_AUD_K3_SRC_SEL>,
+< CLK_TOP_AUD_K4_SRC_SEL>,
+< CLK_TOP_AUD_K1_SRC_DIV>,
+< CLK_TOP_AUD_K2_SRC_DIV>,
+< CLK_TOP_AUD_K3_SRC_DIV>,
+< CLK_TOP_AUD_K4_SRC_DIV>,
+< CLK_TOP_AUD_I2S1_MCLK>,
+< CLK_TOP_AUD_I2S2_MCLK>,
+< CLK_TOP_AUD_I2S3_MCLK>,
+< CLK_TOP_AUD_I2S4_MCLK>,
+< CLK_AUD_I2SO1>,