Re: [PATCH v10 1/2] dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC

2020-05-29 Thread Ramuthevar, Vadivel MuruganX 

Hi Rob,

On 30/5/2020 3:31 am, Rob Herring wrote:

On Thu, May 28, 2020 at 11:39:28PM +0800, Ramuthevar,Vadivel MuruganX wrote:

From: Ramuthevar Vadivel Murugan

Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.

Signed-off-by: Ramuthevar Vadivel 
Murugan
---
  .../devicetree/bindings/mtd/intel,lgm-nand.yaml| 93 ++
  1 file changed, 93 insertions(+)
  create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml

diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml 
b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
new file mode 100644
index ..afecc9920e04
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id:http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml#
+$schema:http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel LGM SoC NAND Controller Device Tree Bindings
+
+allOf:
+  - $ref: "nand-controller.yaml"
+
+maintainers:
+  - Ramuthevar Vadivel Murugan
+
+properties:
+  compatible:
+const: intel,lgm-nand-controller

Doesn't match the example.

Thank you for the review comments...

if we add the compatible = intel,lgm-nand-controller it throws an error 
like below..


/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mtd/intel,lgm-nand.example.dt.yaml: 
nand-controller@e0f0: '#address-cells', '#size-cells' do not match 
any of the regexes: '^nand@[a-f0-9]+$', 'pinctrl-[0-9]+'
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mtd/intel,lgm-nand.example.dt.yaml: 
nand-controller@e0f0: nand@0: '#address-cells', '#size-cells', 
'nand-on-flash-bbt' do not match any of the regexes: 'pinctrl-[0-9]+'


referred from this file 
:Documentation/devicetree/bindings/mtd/nand-controller.yaml


fixed the compatible and example doesn't match issue.

Regards
Vadivel

Re: [PATCH v10 1/2] dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC

2020-05-29 Thread Rob Herring 
On Thu, May 28, 2020 at 11:39:28PM +0800, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan 
> 
> Add YAML file for dt-bindings to support NAND Flash Controller
> on Intel's Lightning Mountain SoC.
> 
> Signed-off-by: Ramuthevar Vadivel Murugan 
> 
> ---
>  .../devicetree/bindings/mtd/intel,lgm-nand.yaml| 93 
> ++
>  1 file changed, 93 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
> 
> diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml 
> b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
> new file mode 100644
> index ..afecc9920e04
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
> @@ -0,0 +1,93 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel LGM SoC NAND Controller Device Tree Bindings
> +
> +allOf:
> +  - $ref: "nand-controller.yaml"
> +
> +maintainers:
> +  - Ramuthevar Vadivel Murugan 
> +
> +properties:
> +  compatible:
> +const: intel,lgm-nand-controller

Doesn't match the example.

> +
> +  reg:
> +maxItems: 6
> +
> +  reg-names:
> +items:
> +   - const: ebunand
> +   - const: hsnand
> +   - const: nand_cs0
> +   - const: nand_cs1
> +   - const: addr_sel0
> +   - const: addr_sel1
> +
> +  clocks:
> +maxItems: 1
> +
> +  dmas:
> +maxItems: 2
> +
> +  dma-names:
> +items:
> +  - const: tx
> +  - const: rx
> +
> +patternProperties:
> +  "^nand@[a-f0-9]+$":
> +type: object
> +properties:
> +  reg:
> +minimum: 0
> +maximum: 7
> +
> +  nand-ecc-mode: true
> +
> +  nand-ecc-algo:
> +const: hw
> +
> +additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - clocks
> +  - dmas
> +  - dma-names
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +nand-controller@e0f0 {
> +  compatible = "intel,lgm-nand";
> +  reg = <0xe0f0 0x100>,
> +<0xe100 0x300>,
> +<0xe140 0x8000>,
> +<0xe1c0 0x1000>,
> +<0x1740 0x4>,
> +<0x17c0 0x4>;
> +  reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1",
> +"addr_sel0", "addr_sel1";
> +  clocks = < 125>;
> +  dmas = < 8>, < 9>;
> +  dma-names = "tx", "rx";
> +  #address-cells = <1>;
> +  #size-cells = <0>;
> +
> +  nand@0 {
> +reg = <0>;
> +nand-on-flash-bbt;
> +#address-cells = <1>;
> +#size-cells = <1>;
> +  };
> +};
> +
> +...
> -- 
> 2.11.0
>

[PATCH v10 1/2] dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC

2020-05-28 Thread Ramuthevar,Vadivel MuruganX 
From: Ramuthevar Vadivel Murugan 

Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.

Signed-off-by: Ramuthevar Vadivel Murugan 

---
 .../devicetree/bindings/mtd/intel,lgm-nand.yaml| 93 ++
 1 file changed, 93 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml

diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml 
b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
new file mode 100644
index ..afecc9920e04
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel LGM SoC NAND Controller Device Tree Bindings
+
+allOf:
+  - $ref: "nand-controller.yaml"
+
+maintainers:
+  - Ramuthevar Vadivel Murugan 
+
+properties:
+  compatible:
+const: intel,lgm-nand-controller
+
+  reg:
+maxItems: 6
+
+  reg-names:
+items:
+   - const: ebunand
+   - const: hsnand
+   - const: nand_cs0
+   - const: nand_cs1
+   - const: addr_sel0
+   - const: addr_sel1
+
+  clocks:
+maxItems: 1
+
+  dmas:
+maxItems: 2
+
+  dma-names:
+items:
+  - const: tx
+  - const: rx
+
+patternProperties:
+  "^nand@[a-f0-9]+$":
+type: object
+properties:
+  reg:
+minimum: 0
+maximum: 7
+
+  nand-ecc-mode: true
+
+  nand-ecc-algo:
+const: hw
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - dmas
+  - dma-names
+
+additionalProperties: false
+
+examples:
+  - |
+nand-controller@e0f0 {
+  compatible = "intel,lgm-nand";
+  reg = <0xe0f0 0x100>,
+<0xe100 0x300>,
+<0xe140 0x8000>,
+<0xe1c0 0x1000>,
+<0x1740 0x4>,
+<0x17c0 0x4>;
+  reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1",
+"addr_sel0", "addr_sel1";
+  clocks = < 125>;
+  dmas = < 8>, < 9>;
+  dma-names = "tx", "rx";
+  #address-cells = <1>;
+  #size-cells = <0>;
+
+  nand@0 {
+reg = <0>;
+nand-on-flash-bbt;
+#address-cells = <1>;
+#size-cells = <1>;
+  };
+};
+
+...
-- 
2.11.0