RE: [PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit

[Andrejczuk, Grzegorz]

>
> This last define is not used anywhere. I told you before, but addressing my 
> review comments completely is an unduly burden, or what?
>

I left to be consistent with the rest of the file. I will remove the line. 

RE: [PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit

[Andrejczuk, Grzegorz]

>
> This last define is not used anywhere. I told you before, but addressing my 
> review comments completely is an unduly burden, or what?
>

I left to be consistent with the rest of the file. I will remove the line. 

Re: [PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit

[Thomas Gleixner]

On Tue, 20 Dec 2016, Grzegorz Andrejczuk wrote:
> 
> diff --git a/arch/x86/include/asm/msr-index.h 
> b/arch/x86/include/asm/msr-index.h
> index 78f3760..55ffae0 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -539,6 +539,12 @@
>  #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
>  #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 
> MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
>  
> +/* MISC_FEATURE_ENABLES non-architectural features */
> +#define MSR_MISC_FEATURE_ENABLES 0x0140
> +
> +#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT  1
> +#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT  (1ULL << 
> MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT)
> +

This last define is not used anywhere. I told you before, but addressing my
review comments completely is an unduly burden, or what?

Thanks,

tglx

Re: [PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit

[Thomas Gleixner]

On Tue, 20 Dec 2016, Grzegorz Andrejczuk wrote:
> 
> diff --git a/arch/x86/include/asm/msr-index.h 
> b/arch/x86/include/asm/msr-index.h
> index 78f3760..55ffae0 100644
> --- a/arch/x86/include/asm/msr-index.h
> +++ b/arch/x86/include/asm/msr-index.h
> @@ -539,6 +539,12 @@
>  #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39
>  #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 
> MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
>  
> +/* MISC_FEATURE_ENABLES non-architectural features */
> +#define MSR_MISC_FEATURE_ENABLES 0x0140
> +
> +#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT  1
> +#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT  (1ULL << 
> MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT)
> +

This last define is not used anywhere. I told you before, but addressing my
review comments completely is an unduly burden, or what?

Thanks,

tglx

[PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit

[Grzegorz Andrejczuk]

Define new MSR MISC_FEATURE_ENABLES (0x140).
On supported CPUs if bit 1 of this new register is set,
then calling MONITOR and MWAIT instructions outside of ring 0 will
not cause invalid-opcode exception.

The MSR MISC_FEATURE_ENABLES is not yet documented in the SDM. Here is
the relevant documentation:

Hex   Dec  Name Scope
140H  320  MISC_FEATURE_ENABLES Thread
   0Reserved
   1If set to 1, the MONITOR and MWAIT instructions do not
cause invalid-opcode exceptions when executed with CPL > 0
or in virtual-8086 mode. If MWAIT is executed when CPL > 0
or in virtual-8086 mode, and if EAX indicates a C-state
other than C0 or C1, the instruction operates as if EAX
indicated the C-state C1.
   63:2 Reserved

Signed-off-by: Grzegorz Andrejczuk 
---
 arch/x86/include/asm/msr-index.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 78f3760..55ffae0 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -539,6 +539,12 @@
 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT   39
 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE   (1ULL << 
MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
 
+/* MISC_FEATURE_ENABLES non-architectural features */
+#define MSR_MISC_FEATURE_ENABLES   0x0140
+
+#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT1
+#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT(1ULL << 
MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT)
+
 #define MSR_IA32_TSC_DEADLINE  0x06E0
 
 /* P4/Xeon+ specific */
-- 
2.5.1

[PATCH v11 1/5] x86/msr: add MSR_MISC_FEATURE_ENABLES and RING3MWAIT bit

[Grzegorz Andrejczuk]

Define new MSR MISC_FEATURE_ENABLES (0x140).
On supported CPUs if bit 1 of this new register is set,
then calling MONITOR and MWAIT instructions outside of ring 0 will
not cause invalid-opcode exception.

The MSR MISC_FEATURE_ENABLES is not yet documented in the SDM. Here is
the relevant documentation:

Hex   Dec  Name Scope
140H  320  MISC_FEATURE_ENABLES Thread
   0Reserved
   1If set to 1, the MONITOR and MWAIT instructions do not
cause invalid-opcode exceptions when executed with CPL > 0
or in virtual-8086 mode. If MWAIT is executed when CPL > 0
or in virtual-8086 mode, and if EAX indicates a C-state
other than C0 or C1, the instruction operates as if EAX
indicated the C-state C1.
   63:2 Reserved

Signed-off-by: Grzegorz Andrejczuk 
---
 arch/x86/include/asm/msr-index.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 78f3760..55ffae0 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -539,6 +539,12 @@
 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT   39
 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE   (1ULL << 
MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT)
 
+/* MISC_FEATURE_ENABLES non-architectural features */
+#define MSR_MISC_FEATURE_ENABLES   0x0140
+
+#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT1
+#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT(1ULL << 
MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT)
+
 #define MSR_IA32_TSC_DEADLINE  0x06E0
 
 /* P4/Xeon+ specific */
-- 
2.5.1