From: Radhey Shyam Pandey
Introduce bindings for TCM memory address space on AMD-xilinx Zynq
UltraScale+ platform. It will help in defining TCM in device-tree
and make it's access platform agnostic and data-driven.
Tightly-coupled memories(TCMs) are low-latency memory that provides
predictable instruction execution and predictable data load/store
timing. Each Cortex-R5F processor contains two 64-bit wide 64 KB memory
banks on the ATCM and BTCM ports, for a total of 128 KB of memory.
The TCM resources(reg, reg-names and power-domain) are documented for
each TCM in the R5 node. The reg and reg-names are made as required
properties as we don't want to hardcode TCM addresses for future
platforms and for zu+ legacy implementation will ensure that the
old dts w/o reg/reg-names works and stable ABI is maintained.
It also extends the examples for TCM split and lockstep modes.
Signed-off-by: Radhey Shyam Pandey
Signed-off-by: Tanmay Shah
---
Changes in v14:
- Remove previous RB tag
- Add xlnx,tcm-mode property
- Add Versal platform support
- Add Versal-NET platform support
.../remoteproc/xlnx,zynqmp-r5fss.yaml | 279 --
1 file changed, 257 insertions(+), 22 deletions(-)
diff --git
a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml
b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml
index 78aac69f1060..6f13da11f593 100644
--- a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml
@@ -18,11 +18,26 @@ description: |
properties:
compatible:
-const: xlnx,zynqmp-r5fss
+enum:
+ - xlnx,zynqmp-r5fss
+ - xlnx,versal-r5fss
+ - xlnx,versal-net-r52fss
+
+ "#address-cells":
+const: 2
+
+ "#size-cells":
+const: 2
+
+ ranges:
+description: |
+ Standard ranges definition providing address translations for
+ local R5F TCM address spaces to bus addresses.
xlnx,cluster-mode:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
+default: 1
description: |
The RPU MPCore can operate in split mode (Dual-processor performance),
Safety
lock-step mode(Both RPU cores execute the same code in lock-step,
@@ -36,8 +51,16 @@ properties:
1: lockstep mode (default)
2: single cpu mode
+ xlnx,tcm-mode:
+$ref: /schemas/types.yaml#/definitions/uint32
+enum: [0, 1]
+description: |
+ Configure RPU TCM
+ 0: split mode
+ 1: lockstep mode
+
patternProperties:
- "^r5f-[a-f0-9]+$":
+ "^r(.*)@[0-9a-f]+$":
type: object
description: |
The RPU is located in the Low Power Domain of the Processor Subsystem.
@@ -52,10 +75,22 @@ patternProperties:
properties:
compatible:
-const: xlnx,zynqmp-r5f
+enum:
+ - xlnx,zynqmp-r5f
+ - xlnx,versal-r5f
+ - xlnx,versal-net-r52f
+
+ reg:
+minItems: 1
+maxItems: 4
+
+ reg-names:
+minItems: 1
+maxItems: 4
power-domains:
-maxItems: 1
+minItems: 2
+maxItems: 5
mboxes:
minItems: 1
@@ -101,35 +136,235 @@ patternProperties:
required:
- compatible
+ - reg
+ - reg-names
- power-domains
-unevaluatedProperties: false
-
required:
- compatible
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+allOf:
+ - if:
+ properties:
+compatible:
+ contains:
+enum:
+ - xlnx,versal-net-r52fss
+then:
+ properties:
+xlnx,tcm-mode: false
+
+ patternProperties:
+"^r52f@[0-9a-f]+$":
+ type: object
+
+ properties:
+reg:
+ minItems: 1
+ items:
+- description: ATCM internal memory
+- description: BTCM internal memory
+- description: CTCM internal memory
+
+reg-names:
+ minItems: 1
+ items:
+- const: atcm0
+- const: btcm0
+- const: ctcm0
+
+power-domains:
+ minItems: 2
+ items:
+- description: RPU core power domain
+- description: ATCM power domain
+- description: BTCM power domain
+- description: CTCM power domain
+
+ - if:
+ properties:
+compatible:
+ contains:
+enum:
+ - xlnx,zynqmp-r5fss
+ - xlnx,versal-r5fss
+then:
+ if:
+properties:
+ xlnx,cluster-mode:
+enum: [1, 2]
+ then:
+properties:
+ xlnx,tcm-mode:
+enum: [1]
+
+patternProperties:
+ "^r5f@[0-9a-f]+$":
+type: object
+
+properties:
+ reg:
+minItems: 1
+items:
+ - description: ATCM
