Re: [PATCH v2] Add TI CDCE925 I2C controlled clock synthesizer driver
On 28-05-15 23:48, Michael Turquette wrote:
Hi Mike,
Quoting Mike Looijmans (2014-12-03 23:26:15)
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and Y3 derive from PLL1
Y4 and Y5 derive from PLL2
Given a target output frequency, the driver will set the PLL and
divider to best approximate the desired output.
Signed-off-by: Mike Looijmans
Sorry for the delay reviewing this. I flagged it for review a while back
and then lost track of it. There is a new-ish mailing list for clock
stuff: linux-...@vger.kernel.org. Please send the next version there,
Cc'ing myself and Stephen Boyd
Okay, will do that. I'll be composing v2 soon.
The biggest changes I highlight below are for the DT binding
description. Otherwise the bulk of the driver looks OK, aside from some
cosmetic bits.
---
v2: Coding style check
Add devicetree binding documentation
.../devicetree/bindings/clock/cdce925.txt | 61 ++
drivers/clk/Kconfig| 17 +
drivers/clk/Makefile |1 +
drivers/clk/clk-cdce925.c | 792
4 files changed, 871 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/cdce925.txt
create mode 100644 drivers/clk/clk-cdce925.c
diff --git a/Documentation/devicetree/bindings/clock/cdce925.txt
b/Documentation/devicetree/bindings/clock/cdce925.txt
new file mode 100644
index 000..0eac770
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/cdce925.txt
@@ -0,0 +1,61 @@
+Binding for TO CDCE925 programmable I2C clock synthesizers.
+
+Reference
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] http://www.ti.com/product/cdce925
+
+Required properties:
+ - compatible: Shall be one of "cdce925", "cdce925pw",
I think the vendor string is supposed to go here to prevent name space
collision. E.g.:
"ti,cdce925"
DT People please correct me if I am wrong.
From experience with other drivers, yes, I think it needs a "ti" prefix here.
+ - reg: I2C device address.
+ - clocks: Points to a fixed parent clock that provides the input frequency.
+ - #clock-cells: From common clock bindings: Shall be 1.
+
+Optional properties:
+ - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
+ board, or to compensate for external influences.
OK, makes sense to expose xtal-load-pf in DT since it may vary per
board.
Until someone wants to dynamically control this to compensate for temperature
drift. But we'll cross that bridge when we find it...
+
+
+For each connected output Y1 through Y5, a child node should be provided. Each
+child node must have the following properties:
+ - #clock-cells: From common clock bindings: Shall be 0.
+Optional properties for the output nodes:
+ - clock-frequency: Output frequency to generate. This defines the output
+ frequency set during boot. It can be reprogrammed during
+ runtime through the common clock framework.
+
+For both PLL1 and PLL2 an optional child node can be used to specify spread
+spectrum clocking parameters.
+ - spread-spectrum: SSC mode as defined in the data sheet.
+ - spread-spectrum-center: Use "centered" mode instead of "max" mode. When
this
+is present, the clock runs at the requested frequency on average.
I'm not sure these should be exposed in the binding description. Can the
clock driver make the determination for which mode to enable? An
interesting idea is to use the new clk_set_rate_range to control this
function.
Also I'm a bit confused about having the two parameters. Isn't "center"
one of the modes? Is the second property needed?
Spread-spectrum adds "noise" to the output frequency. When the SSC level is
set to 1% for example, the "center" mode boolean switch selects between
oscillating within [freq-1%,freq] or [freq-0.5%,freq+0.5%].
Since SSC is mostly used to make a board pass electrical interference tests, I
considered it more of a "board" property than something a clock client would
want to be aware of.
I don't think "clk_set_rate_range" is appropriate here, that is supposed to
set the clock to a constant frequency between two levels. This would map on
something akin to "clk_set_accuracy" if such a thing existed.
+
+
+Example:
+
+ clockgen: cdce925pw@64 {
+ compatible = "cdce925";
+ reg = <0x64>;
+ clocks = <&xtal_27Mhz>;
+ xtal-load-pf = <5>;
+ #clock-cells = <1>;
+ /* PLL options to get SSC 1% centered */
+ PLL2 {
+ spread-spectrum = <4>;
+ spread-s
Re: [PATCH v2] Add TI CDCE925 I2C controlled clock synthesizer driver
Hello,
I was wondering what happened to this patch? Should I resubmit?
Mike.
On 04-12-14 08:26, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and Y3 derive from PLL1
Y4 and Y5 derive from PLL2
Given a target output frequency, the driver will set the PLL and
divider to best approximate the desired output.
Signed-off-by: Mike Looijmans
---
v2: Coding style check
Add devicetree binding documentation
.../devicetree/bindings/clock/cdce925.txt | 61 ++
drivers/clk/Kconfig| 17 +
drivers/clk/Makefile |1 +
drivers/clk/clk-cdce925.c | 792
4 files changed, 871 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/cdce925.txt
create mode 100644 drivers/clk/clk-cdce925.c
diff --git a/Documentation/devicetree/bindings/clock/cdce925.txt
b/Documentation/devicetree/bindings/clock/cdce925.txt
new file mode 100644
index 000..0eac770
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/cdce925.txt
@@ -0,0 +1,61 @@
+Binding for TO CDCE925 programmable I2C clock synthesizers.
+
+Reference
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] http://www.ti.com/product/cdce925
+
+Required properties:
+ - compatible: Shall be one of "cdce925", "cdce925pw",
+ - reg: I2C device address.
+ - clocks: Points to a fixed parent clock that provides the input frequency.
+ - #clock-cells: From common clock bindings: Shall be 1.
+
+Optional properties:
+ - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
+ board, or to compensate for external influences.
+
+
+For each connected output Y1 through Y5, a child node should be provided. Each
+child node must have the following properties:
+ - #clock-cells: From common clock bindings: Shall be 0.
+Optional properties for the output nodes:
+ - clock-frequency: Output frequency to generate. This defines the output
+ frequency set during boot. It can be reprogrammed during
+ runtime through the common clock framework.
+
+For both PLL1 and PLL2 an optional child node can be used to specify spread
+spectrum clocking parameters.
+ - spread-spectrum: SSC mode as defined in the data sheet.
+ - spread-spectrum-center: Use "centered" mode instead of "max" mode. When
this
+is present, the clock runs at the requested frequency on average.
+
+
+Example:
+
+ clockgen: cdce925pw@64 {
+ compatible = "cdce925";
+ reg = <0x64>;
+ clocks = <&xtal_27Mhz>;
+ xtal-load-pf = <5>;
+ #clock-cells = <1>;
+ /* PLL options to get SSC 1% centered */
+ PLL2 {
+ spread-spectrum = <4>;
+ spread-spectrum-center;
+ };
+ /* Outputs calculate mux and divider settings */
+ Y1 {
+ #clock-cells = <0>;
+ clock-frequency = <27000>;
+ };
+ audio_clock: Y2 {
+ #clock-cells = <0>;
+ clock-frequency = <12288000>; /* SPDIF audio */
+ };
+ hdmi_pixel_clock: Y4 {
+ #clock-cells = <0>;
+ clock-frequency = <14850>; /* HD-video */
+ };
+ };
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 455fd17..4e474b3 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -77,6 +77,23 @@ config COMMON_CLK_SI570
This driver supports Silicon Labs 570/571/598/599 programmable
clock generators.
+config COMMON_CLK_CDCE925
+ tristate "Clock driver for TI CDCE925 devices"
+ depends on I2C
+ depends on OF
+ select REGMAP_I2C
+ help
+ ---help---
+ This driver supports the TI CDCE925 programmable clock synthesizer.
+ The chip contains two PLLs with spread-spectrum clocking support and
+ five output dividers. The driver only supports the following setup,
+ and uses a fixed setting for the output muxes.
+ Y1 is derived from the input clock
+ Y2 and Y3 derive from PLL1
+ Y4 and Y5 derive from PLL2
+ Given a target output frequency, the driver will set the PLL and
+ divider to best approximate the desired output.
+
config COMMON_CLK_S2MPS11
tristate "Clock driver for S2MPS1X/S5M8767 MFD"
depends on MFD_SEC_CORE
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d5fba5b..c476066 100644
--- a/drivers/clk/Makefi
Re: [PATCH v2] Add TI CDCE925 I2C controlled clock synthesizer driver
On 12-01-15 04:04, Mike Turquette wrote:
On Thu, Jan 8, 2015 at 11:01 PM, Mike Looijmans wrote:
Just a ping to inform if you've had had time to look at this?
Its in the queue for review this week. A lot to catch up on after the
holidays. Thanks for the ping.
Just another ping, you haven't forgotten me I hope?
We're using this chip on several boards now, and we'd really like to get all
the drivers "mainlined".
M.
On 12/04/2014 08:26 AM, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and Y3 derive from PLL1
Y4 and Y5 derive from PLL2
Given a target output frequency, the driver will set the PLL and
divider to best approximate the desired output.
Signed-off-by: Mike Looijmans
---
v2: Coding style check
Add devicetree binding documentation
.../devicetree/bindings/clock/cdce925.txt | 61 ++
drivers/clk/Kconfig| 17 +
drivers/clk/Makefile |1 +
drivers/clk/clk-cdce925.c | 792
4 files changed, 871 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/cdce925.txt
create mode 100644 drivers/clk/clk-cdce925.c
diff --git a/Documentation/devicetree/bindings/clock/cdce925.txt
b/Documentation/devicetree/bindings/clock/cdce925.txt
new file mode 100644
index 000..0eac770
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/cdce925.txt
@@ -0,0 +1,61 @@
+Binding for TO CDCE925 programmable I2C clock synthesizers.
+
+Reference
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] http://www.ti.com/product/cdce925
+
+Required properties:
+ - compatible: Shall be one of "cdce925", "cdce925pw",
+ - reg: I2C device address.
+ - clocks: Points to a fixed parent clock that provides the input
frequency.
+ - #clock-cells: From common clock bindings: Shall be 1.
+
+Optional properties:
+ - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on
a
+ board, or to compensate for external influences.
+
+
+For each connected output Y1 through Y5, a child node should be provided.
Each
+child node must have the following properties:
+ - #clock-cells: From common clock bindings: Shall be 0.
+Optional properties for the output nodes:
+ - clock-frequency: Output frequency to generate. This defines the output
+ frequency set during boot. It can be reprogrammed
during
+ runtime through the common clock framework.
+
+For both PLL1 and PLL2 an optional child node can be used to specify
spread
+spectrum clocking parameters.
+ - spread-spectrum: SSC mode as defined in the data sheet.
+ - spread-spectrum-center: Use "centered" mode instead of "max" mode.
When this
+is present, the clock runs at the requested frequency on average.
+
+
+Example:
+
+ clockgen: cdce925pw@64 {
+ compatible = "cdce925";
+ reg = <0x64>;
+ clocks = <&xtal_27Mhz>;
+ xtal-load-pf = <5>;
+ #clock-cells = <1>;
+ /* PLL options to get SSC 1% centered */
+ PLL2 {
+ spread-spectrum = <4>;
+ spread-spectrum-center;
+ };
+ /* Outputs calculate mux and divider settings */
+ Y1 {
+ #clock-cells = <0>;
+ clock-frequency = <27000>;
+ };
+ audio_clock: Y2 {
+ #clock-cells = <0>;
+ clock-frequency = <12288000>; /* SPDIF audio */
+ };
+ hdmi_pixel_clock: Y4 {
+ #clock-cells = <0>;
+ clock-frequency = <14850>; /* HD-video */
+ };
+ };
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 455fd17..4e474b3 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -77,6 +77,23 @@ config COMMON_CLK_SI570
This driver supports Silicon Labs 570/571/598/599 programmable
clock generators.
+config COMMON_CLK_CDCE925
+ tristate "Clock driver for TI CDCE925 devices"
+ depends on I2C
+ depends on OF
+ select REGMAP_I2C
+ help
+ ---help---
+ This driver supports the TI CDCE925 programmable clock
synthesizer.
+ The chip contains two PLLs with spread-spectrum clocking support
and
+ five output dividers. The driver only supports the following
setup,
+ and uses a fixed setting for the output muxes.
+ Y1 is derived from the input clock
+ Y2 and Y3 derive from PLL1
+ Y4 and Y5 derive from
Re: [PATCH v2] Add TI CDCE925 I2C controlled clock synthesizer driver
On Thu, Jan 8, 2015 at 11:01 PM, Mike Looijmans wrote:
> Just a ping to inform if you've had had time to look at this?
Its in the queue for review this week. A lot to catch up on after the
holidays. Thanks for the ping.
Regards,
Mike
>
> Mike.
>
> On 12/04/2014 08:26 AM, Mike Looijmans wrote:
>>
>> This driver supports the TI CDCE925 programmable clock synthesizer.
>> The chip contains two PLLs with spread-spectrum clocking support and
>> five output dividers. The driver only supports the following setup,
>> and uses a fixed setting for the output muxes:
>>Y1 is derived from the input clock
>>Y2 and Y3 derive from PLL1
>>Y4 and Y5 derive from PLL2
>> Given a target output frequency, the driver will set the PLL and
>> divider to best approximate the desired output.
>>
>> Signed-off-by: Mike Looijmans
>> ---
>>
>> v2: Coding style check
>> Add devicetree binding documentation
>>
>> .../devicetree/bindings/clock/cdce925.txt | 61 ++
>> drivers/clk/Kconfig| 17 +
>> drivers/clk/Makefile |1 +
>> drivers/clk/clk-cdce925.c | 792
>>
>> 4 files changed, 871 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/cdce925.txt
>> create mode 100644 drivers/clk/clk-cdce925.c
>>
>> diff --git a/Documentation/devicetree/bindings/clock/cdce925.txt
>> b/Documentation/devicetree/bindings/clock/cdce925.txt
>> new file mode 100644
>> index 000..0eac770
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/cdce925.txt
>> @@ -0,0 +1,61 @@
>> +Binding for TO CDCE925 programmable I2C clock synthesizers.
>> +
>> +Reference
>> +This binding uses the common clock binding[1].
>> +
>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>> +[2] http://www.ti.com/product/cdce925
>> +
>> +Required properties:
>> + - compatible: Shall be one of "cdce925", "cdce925pw",
>> + - reg: I2C device address.
>> + - clocks: Points to a fixed parent clock that provides the input
>> frequency.
>> + - #clock-cells: From common clock bindings: Shall be 1.
>> +
>> +Optional properties:
>> + - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on
>> a
>> + board, or to compensate for external influences.
>> +
>> +
>> +For each connected output Y1 through Y5, a child node should be provided.
>> Each
>> +child node must have the following properties:
>> + - #clock-cells: From common clock bindings: Shall be 0.
>> +Optional properties for the output nodes:
>> + - clock-frequency: Output frequency to generate. This defines the output
>> + frequency set during boot. It can be reprogrammed
>> during
>> + runtime through the common clock framework.
>> +
>> +For both PLL1 and PLL2 an optional child node can be used to specify
>> spread
>> +spectrum clocking parameters.
>> + - spread-spectrum: SSC mode as defined in the data sheet.
>> + - spread-spectrum-center: Use "centered" mode instead of "max" mode.
>> When this
>> +is present, the clock runs at the requested frequency on average.
>> +
>> +
>> +Example:
>> +
>> + clockgen: cdce925pw@64 {
>> + compatible = "cdce925";
>> + reg = <0x64>;
>> + clocks = <&xtal_27Mhz>;
>> + xtal-load-pf = <5>;
>> + #clock-cells = <1>;
>> + /* PLL options to get SSC 1% centered */
>> + PLL2 {
>> + spread-spectrum = <4>;
>> + spread-spectrum-center;
>> + };
>> + /* Outputs calculate mux and divider settings */
>> + Y1 {
>> + #clock-cells = <0>;
>> + clock-frequency = <27000>;
>> + };
>> + audio_clock: Y2 {
>> + #clock-cells = <0>;
>> + clock-frequency = <12288000>; /* SPDIF audio */
>> + };
>> + hdmi_pixel_clock: Y4 {
>> + #clock-cells = <0>;
>> + clock-frequency = <14850>; /* HD-video */
>> + };
>> + };
>> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
>> index 455fd17..4e474b3 100644
>> --- a/drivers/clk/Kconfig
>> +++ b/drivers/clk/Kconfig
>> @@ -77,6 +77,23 @@ config COMMON_CLK_SI570
>> This driver supports Silicon Labs 570/571/598/599 programmable
>> clock generators.
>>
>> +config COMMON_CLK_CDCE925
>> + tristate "Clock driver for TI CDCE925 devices"
>> + depends on I2C
>> + depends on OF
>> + select REGMAP_I2C
>> + help
>> + ---help---
>> + This driver supports the TI CDCE925 programmable clock
>> synthesizer.
>> + The chip contains two PLLs with spread-spectrum clocking support
>> and
>> + five output dividers. The driver only supports the following
>> setup,
>> +
Re: [PATCH v2] Add TI CDCE925 I2C controlled clock synthesizer driver
Just a ping to inform if you've had had time to look at this?
Mike.
On 12/04/2014 08:26 AM, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and Y3 derive from PLL1
Y4 and Y5 derive from PLL2
Given a target output frequency, the driver will set the PLL and
divider to best approximate the desired output.
Signed-off-by: Mike Looijmans
---
v2: Coding style check
Add devicetree binding documentation
.../devicetree/bindings/clock/cdce925.txt | 61 ++
drivers/clk/Kconfig| 17 +
drivers/clk/Makefile |1 +
drivers/clk/clk-cdce925.c | 792
4 files changed, 871 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/cdce925.txt
create mode 100644 drivers/clk/clk-cdce925.c
diff --git a/Documentation/devicetree/bindings/clock/cdce925.txt
b/Documentation/devicetree/bindings/clock/cdce925.txt
new file mode 100644
index 000..0eac770
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/cdce925.txt
@@ -0,0 +1,61 @@
+Binding for TO CDCE925 programmable I2C clock synthesizers.
+
+Reference
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] http://www.ti.com/product/cdce925
+
+Required properties:
+ - compatible: Shall be one of "cdce925", "cdce925pw",
+ - reg: I2C device address.
+ - clocks: Points to a fixed parent clock that provides the input frequency.
+ - #clock-cells: From common clock bindings: Shall be 1.
+
+Optional properties:
+ - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
+ board, or to compensate for external influences.
+
+
+For each connected output Y1 through Y5, a child node should be provided. Each
+child node must have the following properties:
+ - #clock-cells: From common clock bindings: Shall be 0.
+Optional properties for the output nodes:
+ - clock-frequency: Output frequency to generate. This defines the output
+ frequency set during boot. It can be reprogrammed during
+ runtime through the common clock framework.
+
+For both PLL1 and PLL2 an optional child node can be used to specify spread
+spectrum clocking parameters.
+ - spread-spectrum: SSC mode as defined in the data sheet.
+ - spread-spectrum-center: Use "centered" mode instead of "max" mode. When
this
+is present, the clock runs at the requested frequency on average.
+
+
+Example:
+
+ clockgen: cdce925pw@64 {
+ compatible = "cdce925";
+ reg = <0x64>;
+ clocks = <&xtal_27Mhz>;
+ xtal-load-pf = <5>;
+ #clock-cells = <1>;
+ /* PLL options to get SSC 1% centered */
+ PLL2 {
+ spread-spectrum = <4>;
+ spread-spectrum-center;
+ };
+ /* Outputs calculate mux and divider settings */
+ Y1 {
+ #clock-cells = <0>;
+ clock-frequency = <27000>;
+ };
+ audio_clock: Y2 {
+ #clock-cells = <0>;
+ clock-frequency = <12288000>; /* SPDIF audio */
+ };
+ hdmi_pixel_clock: Y4 {
+ #clock-cells = <0>;
+ clock-frequency = <14850>; /* HD-video */
+ };
+ };
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 455fd17..4e474b3 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -77,6 +77,23 @@ config COMMON_CLK_SI570
This driver supports Silicon Labs 570/571/598/599 programmable
clock generators.
+config COMMON_CLK_CDCE925
+ tristate "Clock driver for TI CDCE925 devices"
+ depends on I2C
+ depends on OF
+ select REGMAP_I2C
+ help
+ ---help---
+ This driver supports the TI CDCE925 programmable clock synthesizer.
+ The chip contains two PLLs with spread-spectrum clocking support and
+ five output dividers. The driver only supports the following setup,
+ and uses a fixed setting for the output muxes.
+ Y1 is derived from the input clock
+ Y2 and Y3 derive from PLL1
+ Y4 and Y5 derive from PLL2
+ Given a target output frequency, the driver will set the PLL and
+ divider to best approximate the desired output.
+
config COMMON_CLK_S2MPS11
tristate "Clock driver for S2MPS1X/S5M8767 MFD"
depends on MFD_SEC_CORE
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d5fba5b..c476066 100644
--- a/drivers/clk/Makefile
+
Re: [PATCH v2] Add TI CDCE925 I2C controlled clock synthesizer driver
Just a ping to ask for attention. Anyone care to review, comment or otherwise
provide some feedback?
On 12/04/2014 08:26 AM, Mike Looijmans wrote:
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and Y3 derive from PLL1
Y4 and Y5 derive from PLL2
Given a target output frequency, the driver will set the PLL and
divider to best approximate the desired output.
Signed-off-by: Mike Looijmans
---
v2: Coding style check
Add devicetree binding documentation
.../devicetree/bindings/clock/cdce925.txt | 61 ++
drivers/clk/Kconfig| 17 +
drivers/clk/Makefile |1 +
drivers/clk/clk-cdce925.c | 792
4 files changed, 871 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/cdce925.txt
create mode 100644 drivers/clk/clk-cdce925.c
diff --git a/Documentation/devicetree/bindings/clock/cdce925.txt
b/Documentation/devicetree/bindings/clock/cdce925.txt
new file mode 100644
index 000..0eac770
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/cdce925.txt
@@ -0,0 +1,61 @@
+Binding for TO CDCE925 programmable I2C clock synthesizers.
+
+Reference
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] http://www.ti.com/product/cdce925
+
+Required properties:
+ - compatible: Shall be one of "cdce925", "cdce925pw",
+ - reg: I2C device address.
+ - clocks: Points to a fixed parent clock that provides the input frequency.
+ - #clock-cells: From common clock bindings: Shall be 1.
+
+Optional properties:
+ - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
+ board, or to compensate for external influences.
+
+
+For each connected output Y1 through Y5, a child node should be provided. Each
+child node must have the following properties:
+ - #clock-cells: From common clock bindings: Shall be 0.
+Optional properties for the output nodes:
+ - clock-frequency: Output frequency to generate. This defines the output
+ frequency set during boot. It can be reprogrammed during
+ runtime through the common clock framework.
+
+For both PLL1 and PLL2 an optional child node can be used to specify spread
+spectrum clocking parameters.
+ - spread-spectrum: SSC mode as defined in the data sheet.
+ - spread-spectrum-center: Use "centered" mode instead of "max" mode. When
this
+is present, the clock runs at the requested frequency on average.
+
+
+Example:
+
+ clockgen: cdce925pw@64 {
+ compatible = "cdce925";
+ reg = <0x64>;
+ clocks = <&xtal_27Mhz>;
+ xtal-load-pf = <5>;
+ #clock-cells = <1>;
+ /* PLL options to get SSC 1% centered */
+ PLL2 {
+ spread-spectrum = <4>;
+ spread-spectrum-center;
+ };
+ /* Outputs calculate mux and divider settings */
+ Y1 {
+ #clock-cells = <0>;
+ clock-frequency = <27000>;
+ };
+ audio_clock: Y2 {
+ #clock-cells = <0>;
+ clock-frequency = <12288000>; /* SPDIF audio */
+ };
+ hdmi_pixel_clock: Y4 {
+ #clock-cells = <0>;
+ clock-frequency = <14850>; /* HD-video */
+ };
+ };
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 455fd17..4e474b3 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -77,6 +77,23 @@ config COMMON_CLK_SI570
This driver supports Silicon Labs 570/571/598/599 programmable
clock generators.
+config COMMON_CLK_CDCE925
+ tristate "Clock driver for TI CDCE925 devices"
+ depends on I2C
+ depends on OF
+ select REGMAP_I2C
+ help
+ ---help---
+ This driver supports the TI CDCE925 programmable clock synthesizer.
+ The chip contains two PLLs with spread-spectrum clocking support and
+ five output dividers. The driver only supports the following setup,
+ and uses a fixed setting for the output muxes.
+ Y1 is derived from the input clock
+ Y2 and Y3 derive from PLL1
+ Y4 and Y5 derive from PLL2
+ Given a target output frequency, the driver will set the PLL and
+ divider to best approximate the desired output.
+
config COMMON_CLK_S2MPS11
tristate "Clock driver for S2MPS1X/S5M8767 MFD"
depends on MFD_SEC_CORE
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d5fba5b..c476066 1
[PATCH v2] Add TI CDCE925 I2C controlled clock synthesizer driver
This driver supports the TI CDCE925 programmable clock synthesizer.
The chip contains two PLLs with spread-spectrum clocking support and
five output dividers. The driver only supports the following setup,
and uses a fixed setting for the output muxes:
Y1 is derived from the input clock
Y2 and Y3 derive from PLL1
Y4 and Y5 derive from PLL2
Given a target output frequency, the driver will set the PLL and
divider to best approximate the desired output.
Signed-off-by: Mike Looijmans
---
v2: Coding style check
Add devicetree binding documentation
.../devicetree/bindings/clock/cdce925.txt | 61 ++
drivers/clk/Kconfig| 17 +
drivers/clk/Makefile |1 +
drivers/clk/clk-cdce925.c | 792
4 files changed, 871 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/cdce925.txt
create mode 100644 drivers/clk/clk-cdce925.c
diff --git a/Documentation/devicetree/bindings/clock/cdce925.txt
b/Documentation/devicetree/bindings/clock/cdce925.txt
new file mode 100644
index 000..0eac770
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/cdce925.txt
@@ -0,0 +1,61 @@
+Binding for TO CDCE925 programmable I2C clock synthesizers.
+
+Reference
+This binding uses the common clock binding[1].
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] http://www.ti.com/product/cdce925
+
+Required properties:
+ - compatible: Shall be one of "cdce925", "cdce925pw",
+ - reg: I2C device address.
+ - clocks: Points to a fixed parent clock that provides the input frequency.
+ - #clock-cells: From common clock bindings: Shall be 1.
+
+Optional properties:
+ - xtal-load-pf: Crystal load-capacitor value to fine-tune performance on a
+ board, or to compensate for external influences.
+
+
+For each connected output Y1 through Y5, a child node should be provided. Each
+child node must have the following properties:
+ - #clock-cells: From common clock bindings: Shall be 0.
+Optional properties for the output nodes:
+ - clock-frequency: Output frequency to generate. This defines the output
+ frequency set during boot. It can be reprogrammed during
+ runtime through the common clock framework.
+
+For both PLL1 and PLL2 an optional child node can be used to specify spread
+spectrum clocking parameters.
+ - spread-spectrum: SSC mode as defined in the data sheet.
+ - spread-spectrum-center: Use "centered" mode instead of "max" mode. When
this
+is present, the clock runs at the requested frequency on average.
+
+
+Example:
+
+ clockgen: cdce925pw@64 {
+ compatible = "cdce925";
+ reg = <0x64>;
+ clocks = <&xtal_27Mhz>;
+ xtal-load-pf = <5>;
+ #clock-cells = <1>;
+ /* PLL options to get SSC 1% centered */
+ PLL2 {
+ spread-spectrum = <4>;
+ spread-spectrum-center;
+ };
+ /* Outputs calculate mux and divider settings */
+ Y1 {
+ #clock-cells = <0>;
+ clock-frequency = <27000>;
+ };
+ audio_clock: Y2 {
+ #clock-cells = <0>;
+ clock-frequency = <12288000>; /* SPDIF audio */
+ };
+ hdmi_pixel_clock: Y4 {
+ #clock-cells = <0>;
+ clock-frequency = <14850>; /* HD-video */
+ };
+ };
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 455fd17..4e474b3 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -77,6 +77,23 @@ config COMMON_CLK_SI570
This driver supports Silicon Labs 570/571/598/599 programmable
clock generators.
+config COMMON_CLK_CDCE925
+ tristate "Clock driver for TI CDCE925 devices"
+ depends on I2C
+ depends on OF
+ select REGMAP_I2C
+ help
+ ---help---
+ This driver supports the TI CDCE925 programmable clock synthesizer.
+ The chip contains two PLLs with spread-spectrum clocking support and
+ five output dividers. The driver only supports the following setup,
+ and uses a fixed setting for the output muxes.
+ Y1 is derived from the input clock
+ Y2 and Y3 derive from PLL1
+ Y4 and Y5 derive from PLL2
+ Given a target output frequency, the driver will set the PLL and
+ divider to best approximate the desired output.
+
config COMMON_CLK_S2MPS11
tristate "Clock driver for S2MPS1X/S5M8767 MFD"
depends on MFD_SEC_CORE
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d5fba5b..c476066 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_COMMON_CLK_RK808)+= clk-rk808.o
obj-$(CONFIG_COMMON_CLK_
