DMA addresses for devices on the soc bus must be constrained to the 36
address bits that the bus provides. When no IOMMU is present then this
is easy--DMA addresses are just physical addresses and physical
addresses are (by definition) within the address bits of the bus. When
an IOMMU is present, however, DMA addresses are virtual addresses.
Despite these addresses being virtual, however, they are still
constrained by the 36 address bits of the bus.
Unless dma-ranges is specified, which causes bus_dma_mask to be set, DMA
allocations for devices on the platform_bus will use all 48 address bits
available by the ARM SMMU. Causing addresses to be truncated on the bus.
This patch increases the #size-cells to 2, in order to be able to define
dma-ranges describe the 36 bit DMA capability of the bus, and bumps
While touching all reg properties, addresses are padded to 8 digits.
Signed-off-by: Bjorn Andersson
---
Changes since v1:
- Update commit message per discussion with Doug
- Updated "ranges"
- Rebased ontop of a few additional patches from the mailing list
arch/arm64/boot/dts/qcom/sdm845.dtsi | 265 ++-
1 file changed, 133 insertions(+), 132 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index b5dc7c0e9d5a..56dd4ea5fd12 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -339,14 +339,15 @@
};
soc: soc {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0 0x>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0x10 0>;
+ dma-ranges = <0 0 0 0 0x10 0>;
compatible = "simple-bus";
gcc: clock-controller@10 {
compatible = "qcom,gcc-sdm845";
- reg = <0x10 0x1f>;
+ reg = <0 0x0010 0 0x1f>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@@ -354,7 +355,7 @@
qfprom@784000 {
compatible = "qcom,qfprom";
- reg = <0x784000 0x8ff>;
+ reg = <0 0x00784000 0 0x8ff>;
#address-cells = <1>;
#size-cells = <1>;
@@ -371,25 +372,25 @@
rng: rng@793000 {
compatible = "qcom,prng-ee";
- reg = <0x00793000 0x1000>;
+ reg = <0 0x00793000 0 0x1000>;
clocks = < GCC_PRNG_AHB_CLK>;
clock-names = "core";
};
qupv3_id_0: geniqup@8c {
compatible = "qcom,geni-se-qup";
- reg = <0x8c 0x6000>;
+ reg = <0 0x008c 0 0x6000>;
clock-names = "m-ahb", "s-ahb";
clocks = < GCC_QUPV3_WRAP_0_M_AHB_CLK>,
< GCC_QUPV3_WRAP_0_S_AHB_CLK>;
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
ranges;
status = "disabled";
i2c0: i2c@88 {
compatible = "qcom,geni-i2c";
- reg = <0x88 0x4000>;
+ reg = <0 0x0088 0 0x4000>;
clock-names = "se";
clocks = < GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
@@ -402,7 +403,7 @@
spi0: spi@88 {
compatible = "qcom,geni-spi";
- reg = <0x88 0x4000>;
+ reg = <0 0x0088 0 0x4000>;
clock-names = "se";
clocks = < GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
@@ -415,7 +416,7 @@
uart0: serial@88 {
compatible = "qcom,geni-uart";
- reg = <0x88 0x4000>;
+ reg = <0 0x0088 0 0x4000>;
clock-names = "se";
clocks = < GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
@@ -426,7 +427,7 @@
i2c1: i2c@884000 {
compatible = "qcom,geni-i2c";
- reg = <0x884000 0x4000>;
+ reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
