subject:"\[PATCH v2\] i2c\: vt8500\: Add support for I2C bus on Wondermedia SoCs"

Re: [PATCH v2] i2c: vt8500: Add support for I2C bus on Wondermedia SoCs

2013-06-14 Thread Wolfram Sang

On Wed, Jun 12, 2013 at 07:56:25PM +1200, Tony Prisk wrote:
> This patch adds support for the I2C bus controllers found on Wondermedia
> 8xxx-series SoCs. Only master-mode is supported.
> 
> Signed-off-by: Tony Prisk 
> ---

Please describe here what changed since the last version. It's a lot
easier and faster to review then.

> +static int wmt_i2c_xfer(struct i2c_adapter *adap,
> + struct i2c_msg msgs[],
> + int num)
> +{
> + struct i2c_msg *pmsg;
> + int i, is_last, no_start;
> + int ret = 0;
> +
> + for (i = 0; ret >= 0 && i < num; i++) {
> + is_last = ((i + 1) == num);
> + no_start = (i != 0);

(i != 0) is a restart condition (start instead of stop)...

> +
> + pmsg = [i];
> + if (pmsg->flags & I2C_M_NOSTART)
> + no_start = 1;

...and this is a no_start (concatenating messages). I do have the
impression you are mixing those two?

> + if (pmsg->flags & I2C_M_RD)
> + ret = wmt_i2c_read(adap, pmsg, no_start, is_last);
> + else
> + ret = wmt_i2c_write(adap, pmsg, no_start, is_last);
> + }
> +
> + return (ret < 0) ? ret : i;
> +}
> + adap = _dev->adapter;
> + i2c_set_adapdata(adap, i2c_dev);
> + strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
> + adap->owner = THIS_MODULE;
> + adap->algo = _i2c_algo;
> + adap->dev.parent = >dev;
> + adap->dev.of_node = pdev->dev.of_node;
> + adap->nr = of_alias_get_id(pdev->dev.of_node, "i2c");

Drop this line...

> +
> + init_completion(_dev->complete);
> +
> + err = wmt_i2c_reset_hardware(i2c_dev);
> + if (err) {
> + dev_err(>dev, "error initializing hardware\n");
> + return err;
> + }
> +
> + err = i2c_add_numbered_adapter(adap);

... and use i2c_add_adpter here. Since recently the core checks the
ofnode for an alias. Sorry, forgot to mention this last time.

> + if (err) {
> + dev_err(>dev, "failed to add adapter\n");
> + return err;
> + }
> +
> + platform_set_drvdata(pdev, i2c_dev);
> +
> + of_i2c_register_devices(adap);
> +
> + return 0;
> +}
> +
> +module_platform_driver(wmt_i2c_driver);
> +
> +MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
> +MODULE_AUTHOR("Tony Prisk ");
> +MODULE_LICENSE("GPL and additional rights");

I see no additional rights mentioned. According to the header "GPL"
should do, but you know the original sources better.

> +MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);
> -- 
> 1.7.9.5
> 

Regards,

   Wolfram



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Re: [PATCH v2] i2c: vt8500: Add support for I2C bus on Wondermedia SoCs

2013-06-14 Thread Wolfram Sang

On Wed, Jun 12, 2013 at 07:56:25PM +1200, Tony Prisk wrote:
 This patch adds support for the I2C bus controllers found on Wondermedia
 8xxx-series SoCs. Only master-mode is supported.
 
 Signed-off-by: Tony Prisk li...@prisktech.co.nz
 ---

Please describe here what changed since the last version. It's a lot
easier and faster to review then.

 +static int wmt_i2c_xfer(struct i2c_adapter *adap,
 + struct i2c_msg msgs[],
 + int num)
 +{
 + struct i2c_msg *pmsg;
 + int i, is_last, no_start;
 + int ret = 0;
 +
 + for (i = 0; ret = 0  i  num; i++) {
 + is_last = ((i + 1) == num);
 + no_start = (i != 0);

(i != 0) is a restart condition (start instead of stop)...

 +
 + pmsg = msgs[i];
 + if (pmsg-flags  I2C_M_NOSTART)
 + no_start = 1;

...and this is a no_start (concatenating messages). I do have the
impression you are mixing those two?

 + if (pmsg-flags  I2C_M_RD)
 + ret = wmt_i2c_read(adap, pmsg, no_start, is_last);
 + else
 + ret = wmt_i2c_write(adap, pmsg, no_start, is_last);
 + }
 +
 + return (ret  0) ? ret : i;
 +}
 + adap = i2c_dev-adapter;
 + i2c_set_adapdata(adap, i2c_dev);
 + strlcpy(adap-name, WMT I2C adapter, sizeof(adap-name));
 + adap-owner = THIS_MODULE;
 + adap-algo = wmt_i2c_algo;
 + adap-dev.parent = pdev-dev;
 + adap-dev.of_node = pdev-dev.of_node;
 + adap-nr = of_alias_get_id(pdev-dev.of_node, i2c);

Drop this line...

 +
 + init_completion(i2c_dev-complete);
 +
 + err = wmt_i2c_reset_hardware(i2c_dev);
 + if (err) {
 + dev_err(pdev-dev, error initializing hardware\n);
 + return err;
 + }
 +
 + err = i2c_add_numbered_adapter(adap);

... and use i2c_add_adpter here. Since recently the core checks the
ofnode for an alias. Sorry, forgot to mention this last time.

 + if (err) {
 + dev_err(pdev-dev, failed to add adapter\n);
 + return err;
 + }
 +
 + platform_set_drvdata(pdev, i2c_dev);
 +
 + of_i2c_register_devices(adap);
 +
 + return 0;
 +}
 +
 +module_platform_driver(wmt_i2c_driver);
 +
 +MODULE_DESCRIPTION(Wondermedia I2C master-mode bus adapter);
 +MODULE_AUTHOR(Tony Prisk li...@prisktech.co.nz);
 +MODULE_LICENSE(GPL and additional rights);

I see no additional rights mentioned. According to the header GPL
should do, but you know the original sources better.

 +MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);
 -- 
 1.7.9.5
 

Regards,

   Wolfram



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[PATCH v2] i2c: vt8500: Add support for I2C bus on Wondermedia SoCs

2013-06-12 Thread Tony Prisk

This patch adds support for the I2C bus controllers found on Wondermedia
8xxx-series SoCs. Only master-mode is supported.

Signed-off-by: Tony Prisk 
---
 .../devicetree/bindings/i2c/i2c-vt8500.txt |   24 +
 MAINTAINERS|1 +
 drivers/i2c/busses/Kconfig |   10 +
 drivers/i2c/busses/Makefile|1 +
 drivers/i2c/busses/i2c-wmt.c   |  483 
 5 files changed, 519 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
 create mode 100644 drivers/i2c/busses/i2c-wmt.c

diff --git a/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt 
b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
new file mode 100644
index 000..94a425e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
@@ -0,0 +1,24 @@
+* Wondermedia I2C Controller
+
+Required properties :
+
+ - compatible : should be "wm,wm8505-i2c"
+ - reg : Offset and length of the register set for the device
+ - interrupts :  where IRQ is the interrupt number
+ - clocks : phandle to the I2C clock source
+
+Optional properties :
+
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+   Valid values are 10 and 40.
+   Default to 10 if not specified, or invalid value.
+
+Example :
+
+   i2c_0: i2c@d828 {
+   compatible = "wm,wm8505-i2c";
+   reg = <0xd828 0x1000>;
+   interrupts = <19>;
+   clocks = <>;
+   clock-frequency = <40>;
+   };
diff --git a/MAINTAINERS b/MAINTAINERS
index 3d7782b..44ea994 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1285,6 +1285,7 @@ S:Maintained
 F: arch/arm/mach-vt8500/
 F: drivers/clocksource/vt8500_timer.c
 F: drivers/gpio/gpio-vt8500.c
+F: drivers/i2c/busses/i2c-wmt.c
 F: drivers/mmc/host/wmt-sdmmc.c
 F: drivers/pwm/pwm-vt8500.c
 F: drivers/rtc/rtc-vt8500.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 631736e..89e7ec2 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -724,6 +724,16 @@ config I2C_VERSATILE
  This driver can also be built as a module.  If so, the module
  will be called i2c-versatile.
 
+config I2C_WMT
+   tristate "Wondermedia WM8xxx SoC I2C bus support"
+   depends on ARCH_VT8500
+   help
+ Say yes if you want to support the I2C bus on Wondermedia 8xxx-series
+ SoCs.
+
+ This driver can also be built as a module. If so, the module will be
+ called i2c-wmt.
+
 config I2C_OCTEON
tristate "Cavium OCTEON I2C bus support"
depends on CPU_CAVIUM_OCTEON
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 8f4fc23..3ba94a9 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_I2C_SIRF)+= i2c-sirf.o
 obj-$(CONFIG_I2C_STU300)   += i2c-stu300.o
 obj-$(CONFIG_I2C_TEGRA)+= i2c-tegra.o
 obj-$(CONFIG_I2C_VERSATILE)+= i2c-versatile.o
+obj-$(CONFIG_I2C_WMT)  += i2c-wmt.o
 obj-$(CONFIG_I2C_OCTEON)   += i2c-octeon.o
 obj-$(CONFIG_I2C_XILINX)   += i2c-xiic.o
 obj-$(CONFIG_I2C_XLR)  += i2c-xlr.o
diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c
new file mode 100644
index 000..2bbac9b
--- /dev/null
+++ b/drivers/i2c/busses/i2c-wmt.c
@@ -0,0 +1,483 @@
+/*
+ *  Wondermedia I2C Master Mode Driver
+ *
+ *  Copyright (C) 2012 Tony Prisk 
+ *
+ *  Derived from GPLv2+ licensed source:
+ *  - Copyright (C) 2008 WonderMedia Technologies, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2, or
+ *  (at your option) any later version. as published by the Free Software
+ *  Foundation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define REG_CR 0x00
+#define REG_TCR0x02
+#define REG_CSR0x04
+#define REG_ISR0x06
+#define REG_IMR0x08
+#define REG_CDR0x0A
+#define REG_TR 0x0C
+#define REG_MCR0x0E
+#define REG_SLAVE_CR   0x10
+#define REG_SLAVE_SR   0x12
+#define REG_SLAVE_ISR  0x14
+#define REG_SLAVE_IMR  0x16
+#define REG_SLAVE_DR   0x18
+#define REG_SLAVE_TR   0x1A
+
+/* REG_CR Bit fields */
+#define CR_TX_NEXT_ACK 0x
+#define CR_ENABLE  0x0001
+#define CR_TX_NEXT_NO_ACK  0x0002
+#define CR_TX_END  0x0004
+#define CR_CPU_RDY 0x0008
+#define SLAV_MODE_SEL  0x8000
+
+/* REG_TCR Bit fields */
+#define TCR_STANDARD_MODE  0x
+#define TCR_MASTER_WRITE   0x
+#define TCR_HS_MODE0x2000
+#define TCR_MASTER_READ0x4000
+#define

[PATCH v2] i2c: vt8500: Add support for I2C bus on Wondermedia SoCs

2013-06-12 Thread Tony Prisk

This patch adds support for the I2C bus controllers found on Wondermedia
8xxx-series SoCs. Only master-mode is supported.

Signed-off-by: Tony Prisk li...@prisktech.co.nz
---
 .../devicetree/bindings/i2c/i2c-vt8500.txt |   24 +
 MAINTAINERS|1 +
 drivers/i2c/busses/Kconfig |   10 +
 drivers/i2c/busses/Makefile|1 +
 drivers/i2c/busses/i2c-wmt.c   |  483 
 5 files changed, 519 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
 create mode 100644 drivers/i2c/busses/i2c-wmt.c

diff --git a/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt 
b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
new file mode 100644
index 000..94a425e
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-vt8500.txt
@@ -0,0 +1,24 @@
+* Wondermedia I2C Controller
+
+Required properties :
+
+ - compatible : should be wm,wm8505-i2c
+ - reg : Offset and length of the register set for the device
+ - interrupts : IRQ where IRQ is the interrupt number
+ - clocks : phandle to the I2C clock source
+
+Optional properties :
+
+ - clock-frequency : desired I2C bus clock frequency in Hz.
+   Valid values are 10 and 40.
+   Default to 10 if not specified, or invalid value.
+
+Example :
+
+   i2c_0: i2c@d828 {
+   compatible = wm,wm8505-i2c;
+   reg = 0xd828 0x1000;
+   interrupts = 19;
+   clocks = clki2c0;
+   clock-frequency = 40;
+   };
diff --git a/MAINTAINERS b/MAINTAINERS
index 3d7782b..44ea994 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1285,6 +1285,7 @@ S:Maintained
 F: arch/arm/mach-vt8500/
 F: drivers/clocksource/vt8500_timer.c
 F: drivers/gpio/gpio-vt8500.c
+F: drivers/i2c/busses/i2c-wmt.c
 F: drivers/mmc/host/wmt-sdmmc.c
 F: drivers/pwm/pwm-vt8500.c
 F: drivers/rtc/rtc-vt8500.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 631736e..89e7ec2 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -724,6 +724,16 @@ config I2C_VERSATILE
  This driver can also be built as a module.  If so, the module
  will be called i2c-versatile.
 
+config I2C_WMT
+   tristate Wondermedia WM8xxx SoC I2C bus support
+   depends on ARCH_VT8500
+   help
+ Say yes if you want to support the I2C bus on Wondermedia 8xxx-series
+ SoCs.
+
+ This driver can also be built as a module. If so, the module will be
+ called i2c-wmt.
+
 config I2C_OCTEON
tristate Cavium OCTEON I2C bus support
depends on CPU_CAVIUM_OCTEON
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 8f4fc23..3ba94a9 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_I2C_SIRF)+= i2c-sirf.o
 obj-$(CONFIG_I2C_STU300)   += i2c-stu300.o
 obj-$(CONFIG_I2C_TEGRA)+= i2c-tegra.o
 obj-$(CONFIG_I2C_VERSATILE)+= i2c-versatile.o
+obj-$(CONFIG_I2C_WMT)  += i2c-wmt.o
 obj-$(CONFIG_I2C_OCTEON)   += i2c-octeon.o
 obj-$(CONFIG_I2C_XILINX)   += i2c-xiic.o
 obj-$(CONFIG_I2C_XLR)  += i2c-xlr.o
diff --git a/drivers/i2c/busses/i2c-wmt.c b/drivers/i2c/busses/i2c-wmt.c
new file mode 100644
index 000..2bbac9b
--- /dev/null
+++ b/drivers/i2c/busses/i2c-wmt.c
@@ -0,0 +1,483 @@
+/*
+ *  Wondermedia I2C Master Mode Driver
+ *
+ *  Copyright (C) 2012 Tony Prisk li...@prisktech.co.nz
+ *
+ *  Derived from GPLv2+ licensed source:
+ *  - Copyright (C) 2008 WonderMedia Technologies, Inc.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2, or
+ *  (at your option) any later version. as published by the Free Software
+ *  Foundation
+ */
+
+#include linux/clk.h
+#include linux/delay.h
+#include linux/err.h
+#include linux/i2c.h
+#include linux/interrupt.h
+#include linux/io.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/of_i2c.h
+#include linux/of_irq.h
+#include linux/platform_device.h
+
+#define REG_CR 0x00
+#define REG_TCR0x02
+#define REG_CSR0x04
+#define REG_ISR0x06
+#define REG_IMR0x08
+#define REG_CDR0x0A
+#define REG_TR 0x0C
+#define REG_MCR0x0E
+#define REG_SLAVE_CR   0x10
+#define REG_SLAVE_SR   0x12
+#define REG_SLAVE_ISR  0x14
+#define REG_SLAVE_IMR  0x16
+#define REG_SLAVE_DR   0x18
+#define REG_SLAVE_TR   0x1A
+
+/* REG_CR Bit fields */
+#define CR_TX_NEXT_ACK 0x
+#define CR_ENABLE  0x0001
+#define CR_TX_NEXT_NO_ACK  0x0002
+#define CR_TX_END  0x0004
+#define CR_CPU_RDY 0x0008
+#define SLAV_MODE_SEL  0x8000
+
+/*

Re: [PATCH v2] i2c: vt8500: Add support for I2C bus on Wondermedia SoCs

Re: [PATCH v2] i2c: vt8500: Add support for I2C bus on Wondermedia SoCs

[PATCH v2] i2c: vt8500: Add support for I2C bus on Wondermedia SoCs

[PATCH v2] i2c: vt8500: Add support for I2C bus on Wondermedia SoCs

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