Re: [PATCH v2 04/15] ARM: milbeaut: Add basic support for Milbeaut m10v SoC

2019-02-19 Thread Sugaya, Taichi 

Hi,

On 2019/02/19 18:21, Arnd Bergmann wrote:

On Tue, Feb 19, 2019 at 8:12 AM Sugaya, Taichi
 wrote:

On 2019/02/18 21:15, Arnd Bergmann wrote:

On Fri, Feb 8, 2019 at 1:26 PM Sugaya Taichi
 wrote:



+static int __init m10v_pm_init(void)
+{
+   suspend_set_ops(&m10v_pm_ops);
+
+   return 0;
+}
+late_initcall(m10v_pm_init);


This requires a check to ensure you are actually on the right platform,
otherwise you break suspend/resume in a multiplatform kernel running
on anything other than milbeaut.



OK.
I think the solution is adding a "if statement with mlbeaut compatible"
above suspend_set_ops(&m10v_pm_ops).


Right, you can either use a call to of_machine_is_compatible(),
or you add a machine descriptor with OF_MACHINE_START()
and use this as the init_late() callback.



Yeah, I will use "of_machine_is_compatible()".

Thanks,
Sugaya Taichi


   Arnd

Re: [PATCH v2 04/15] ARM: milbeaut: Add basic support for Milbeaut m10v SoC

2019-02-19 Thread Arnd Bergmann 
On Tue, Feb 19, 2019 at 8:12 AM Sugaya, Taichi
 wrote:
> On 2019/02/18 21:15, Arnd Bergmann wrote:
> > On Fri, Feb 8, 2019 at 1:26 PM Sugaya Taichi
> >  wrote:
>
> >> +static int __init m10v_pm_init(void)
> >> +{
> >> +   suspend_set_ops(&m10v_pm_ops);
> >> +
> >> +   return 0;
> >> +}
> >> +late_initcall(m10v_pm_init);
> >
> > This requires a check to ensure you are actually on the right platform,
> > otherwise you break suspend/resume in a multiplatform kernel running
> > on anything other than milbeaut.
> >
>
> OK.
> I think the solution is adding a "if statement with mlbeaut compatible"
> above suspend_set_ops(&m10v_pm_ops).

Right, you can either use a call to of_machine_is_compatible(),
or you add a machine descriptor with OF_MACHINE_START()
and use this as the init_late() callback.

  Arnd

Re: [PATCH v2 04/15] ARM: milbeaut: Add basic support for Milbeaut m10v SoC

2019-02-18 Thread Sugaya, Taichi 

Hi,

Thank you for your comments.

On 2019/02/18 21:15, Arnd Bergmann wrote:

On Fri, Feb 8, 2019 at 1:26 PM Sugaya Taichi
 wrote:


+static int m10v_pm_enter(suspend_state_t state)
+{
+   switch (state) {
+   case PM_SUSPEND_STANDBY:
+   pr_err("STANDBY\n");
+   asm("wfi");
+   break;
+   case PM_SUSPEND_MEM:
+   pr_err("SUSPEND\n");
+   cpu_pm_enter();
+   cpu_suspend(0, m10v_die);
+   cpu_pm_exit();
+   break;
+   }
+   return 0;
+}


It looks like you left the pr_err() messages from bringup, they should probably
be removed now.



OK. remove the pr_err()s.



+static int __init m10v_pm_init(void)
+{
+   suspend_set_ops(&m10v_pm_ops);
+
+   return 0;
+}
+late_initcall(m10v_pm_init);


This requires a check to ensure you are actually on the right platform,
otherwise you break suspend/resume in a multiplatform kernel running
on anything other than milbeaut.



OK.
I think the solution is adding a "if statement with mlbeaut compatible" 
above suspend_set_ops(&m10v_pm_ops).


Thanks,
Sugaya Taichi



Arnd

Re: [PATCH v2 04/15] ARM: milbeaut: Add basic support for Milbeaut m10v SoC

2019-02-18 Thread Arnd Bergmann 
On Fri, Feb 8, 2019 at 1:26 PM Sugaya Taichi
 wrote:

> +static int m10v_pm_enter(suspend_state_t state)
> +{
> +   switch (state) {
> +   case PM_SUSPEND_STANDBY:
> +   pr_err("STANDBY\n");
> +   asm("wfi");
> +   break;
> +   case PM_SUSPEND_MEM:
> +   pr_err("SUSPEND\n");
> +   cpu_pm_enter();
> +   cpu_suspend(0, m10v_die);
> +   cpu_pm_exit();
> +   break;
> +   }
> +   return 0;
> +}

It looks like you left the pr_err() messages from bringup, they should probably
be removed now.

> +static int __init m10v_pm_init(void)
> +{
> +   suspend_set_ops(&m10v_pm_ops);
> +
> +   return 0;
> +}
> +late_initcall(m10v_pm_init);

This requires a check to ensure you are actually on the right platform,
otherwise you break suspend/resume in a multiplatform kernel running
on anything other than milbeaut.

   Arnd

[PATCH v2 04/15] ARM: milbeaut: Add basic support for Milbeaut m10v SoC

2019-02-08 Thread Sugaya Taichi 
This adds the basic M10V SoC support under arch/arm.
Since all cores are activated in the custom bootloader before booting
linux, it is necessary to wait for the secondary-cores using cpu-enable-
method and special sram.

Signed-off-by: Sugaya Taichi 
---
 arch/arm/Kconfig |   2 +
 arch/arm/Makefile|   1 +
 arch/arm/mach-milbeaut/Kconfig   |  20 ++
 arch/arm/mach-milbeaut/Makefile  |   1 +
 arch/arm/mach-milbeaut/platsmp.c | 144 +++
 5 files changed, 168 insertions(+)
 create mode 100644 arch/arm/mach-milbeaut/Kconfig
 create mode 100644 arch/arm/mach-milbeaut/Makefile
 create mode 100644 arch/arm/mach-milbeaut/platsmp.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 664e918..c8cb752 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -750,6 +750,8 @@ source "arch/arm/mach-mediatek/Kconfig"
 
 source "arch/arm/mach-meson/Kconfig"
 
+source "arch/arm/mach-milbeaut/Kconfig"
+
 source "arch/arm/mach-mmp/Kconfig"
 
 source "arch/arm/mach-moxart/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 9db3c58..0e9 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -190,6 +190,7 @@ machine-$(CONFIG_ARCH_MV78XX0)  += mv78xx0
 machine-$(CONFIG_ARCH_MVEBU)   += mvebu
 machine-$(CONFIG_ARCH_MXC) += imx
 machine-$(CONFIG_ARCH_MEDIATEK)+= mediatek
+machine-$(CONFIG_ARCH_MILBEAUT)+= milbeaut
 machine-$(CONFIG_ARCH_MXS) += mxs
 machine-$(CONFIG_ARCH_NETX)+= netx
 machine-$(CONFIG_ARCH_NOMADIK) += nomadik
diff --git a/arch/arm/mach-milbeaut/Kconfig b/arch/arm/mach-milbeaut/Kconfig
new file mode 100644
index 000..6a576fd
--- /dev/null
+++ b/arch/arm/mach-milbeaut/Kconfig
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0
+menuconfig ARCH_MILBEAUT
+   bool "Socionext Milbeaut SoCs"
+   depends on ARCH_MULTI_V7
+   select ARM_GIC
+   help
+ This enables support for Socionext Milbeaut SoCs
+
+if ARCH_MILBEAUT
+
+config ARCH_MILBEAUT_M10V
+   bool "Milbeaut SC2000/M10V platform"
+   select ARM_ARCH_TIMER
+   select MILBEAUT_TIMER
+   select PINCTRL
+   select PINCTRL_MILBEAUT
+   help
+ Support for Socionext's MILBEAUT M10V based systems
+
+endif
diff --git a/arch/arm/mach-milbeaut/Makefile b/arch/arm/mach-milbeaut/Makefile
new file mode 100644
index 000..ce5ea06
--- /dev/null
+++ b/arch/arm/mach-milbeaut/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_SMP) += platsmp.o
diff --git a/arch/arm/mach-milbeaut/platsmp.c b/arch/arm/mach-milbeaut/platsmp.c
new file mode 100644
index 000..bdcd98e
--- /dev/null
+++ b/arch/arm/mach-milbeaut/platsmp.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright:  (C) 2018 Socionext Inc.
+ * Copyright:  (C) 2015 Linaro Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define M10V_MAX_CPU   4
+#define KERNEL_UNBOOT_FLAG 0x12345678
+
+static void __iomem *m10v_smp_base;
+
+static int m10v_boot_secondary(unsigned int l_cpu, struct task_struct *idle)
+{
+   unsigned int mpidr, cpu, cluster;
+
+   if (!m10v_smp_base)
+   return -ENXIO;
+
+   mpidr = cpu_logical_map(l_cpu);
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+
+   if (cpu >= M10V_MAX_CPU)
+   return -EINVAL;
+
+   pr_info("%s: cpu %u l_cpu %u cluster %u\n",
+   __func__, cpu, l_cpu, cluster);
+
+   writel(__pa_symbol(secondary_startup), m10v_smp_base + cpu * 4);
+   arch_send_wakeup_ipi_mask(cpumask_of(l_cpu));
+
+   return 0;
+}
+
+static void m10v_smp_init(unsigned int max_cpus)
+{
+   unsigned int mpidr, cpu, cluster;
+   struct device_node *np;
+
+   np = of_find_compatible_node(NULL, NULL, "socionext,milbeaut-smp-sram");
+   if (!np)
+   return;
+
+   m10v_smp_base = of_iomap(np, 0);
+   if (!m10v_smp_base)
+   return;
+
+   mpidr = read_cpuid_mpidr();
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+   cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+   pr_info("MCPM boot on cpu_%u cluster_%u\n", cpu, cluster);
+
+   for (cpu = 0; cpu < M10V_MAX_CPU; cpu++)
+   writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
+}
+
+static void m10v_cpu_die(unsigned int l_cpu)
+{
+   gic_cpu_if_down(0);
+   v7_exit_coherency_flush(louis);
+   wfi();
+}
+
+static int m10v_cpu_kill(unsigned int l_cpu)
+{
+   unsigned int mpidr, cpu;
+
+   mpidr = cpu_logical_map(l_cpu);
+   cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+
+   writel(KERNEL_UNBOOT_FLAG, m10v_smp_base + cpu * 4);
+
+   return 1;
+}
+
+static struct smp_operations m10v_smp_ops __initdata = {
+   .smp_prepare_cpus   = m10v_smp_init,
+   .smp_boot_secondary = m10v_boot_secondary,
+   .cpu_die= m1