Re: [PATCH v2 06/10] pwm: pwm-tiehrpwm: Add device-tree binding support for EHRPWM driver
On Thu, Nov 08, 2012 at 01:23:13PM +0530, Philip, Avinash wrote: > This patch > 1. Add support for device-tree binding for EHRWPM driver. > 2. Set size of pwm-cells set to 3 to support PWM channel number, PWM >period & polarity configuration from device tree. > 3. Add enable/disable clock gating in PWM subsystem common config space. > 4. When here set .owner member in platform_driver structure to >THIS_MODULE. > > Signed-off-by: Philip, Avinash > Cc: Grant Likely > Cc: Rob Herring > Cc: Rob Landley > --- > Changes since v1: > - Add separate patch for pinctrl support > - Add conditional check for PWM subsystem clock enable. > - Combined with HWMOD changes & DT bindings. > - Remove the custom of xlate support. > > :00 100644 000... aa2ed0a... A > Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt > :100644 100644 d3c1dff... fba7f9b... Mdrivers/pwm/pwm-tiehrpwm.c > .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 25 ++ > drivers/pwm/pwm-tiehrpwm.c | 49 > +++- > 2 files changed, 72 insertions(+), 2 deletions(-) The same comments apply as for the pwm-tiecap driver patch. Thierry pgp2ryrW5NLON.pgp Description: PGP signature
Re: [PATCH v2 06/10] pwm: pwm-tiehrpwm: Add device-tree binding support for EHRPWM driver
On Thu, Nov 08, 2012 at 01:23:13PM +0530, Philip, Avinash wrote: This patch 1. Add support for device-tree binding for EHRWPM driver. 2. Set size of pwm-cells set to 3 to support PWM channel number, PWM period polarity configuration from device tree. 3. Add enable/disable clock gating in PWM subsystem common config space. 4. When here set .owner member in platform_driver structure to THIS_MODULE. Signed-off-by: Philip, Avinash avinashphi...@ti.com Cc: Grant Likely grant.lik...@secretlab.ca Cc: Rob Herring rob.herr...@calxeda.com Cc: Rob Landley r...@landley.net --- Changes since v1: - Add separate patch for pinctrl support - Add conditional check for PWM subsystem clock enable. - Combined with HWMOD changes DT bindings. - Remove the custom of xlate support. :00 100644 000... aa2ed0a... A Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt :100644 100644 d3c1dff... fba7f9b... Mdrivers/pwm/pwm-tiehrpwm.c .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 25 ++ drivers/pwm/pwm-tiehrpwm.c | 49 +++- 2 files changed, 72 insertions(+), 2 deletions(-) The same comments apply as for the pwm-tiecap driver patch. Thierry pgp2ryrW5NLON.pgp Description: PGP signature
[PATCH v2 06/10] pwm: pwm-tiehrpwm: Add device-tree binding support for EHRPWM driver
This patch 1. Add support for device-tree binding for EHRWPM driver. 2. Set size of pwm-cells set to 3 to support PWM channel number, PWM period & polarity configuration from device tree. 3. Add enable/disable clock gating in PWM subsystem common config space. 4. When here set .owner member in platform_driver structure to THIS_MODULE. Signed-off-by: Philip, Avinash Cc: Grant Likely Cc: Rob Herring Cc: Rob Landley --- Changes since v1: - Add separate patch for pinctrl support - Add conditional check for PWM subsystem clock enable. - Combined with HWMOD changes & DT bindings. - Remove the custom of xlate support. :00 100644 000... aa2ed0a... A Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt :100644 100644 d3c1dff... fba7f9b... M drivers/pwm/pwm-tiehrpwm.c .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 25 ++ drivers/pwm/pwm-tiehrpwm.c | 49 +++- 2 files changed, 72 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt new file mode 100644 index 000..aa2ed0a --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -0,0 +1,25 @@ +TI SOC EHRPWM based PWM controller + +Required properties: +- compatible : Must be "ti,am33xx-ehrpwm" +- #pwm-cells: Should be 3. Number of cells being used to specify PWM property. + First cell specifies the per-chip index of the PWM to use, the second + cell is the period cycle in nanoseconds and bit 0 in the third cell is + used to encode the polarity of PWM output. +- reg: physical base address and size of the registers map. + +Optional properties: +- ti,hwmods: Name of the hwmod associated to the EHRPWM: + "ehrpwm", being the 0-based instance number from the HW spec +- tbclkgating: platforms require tbclk gating from control module + should populate + +Example: + +ehrpwm0: ehrpwm@0 { + compatible = "ti,am33xx-ehrpwm"; + #pwm-cells = <3>; + reg = <0x48300200 0x100>; + ti,hwmods = "ehrpwm0"; + tbclkgating; +}; diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index d3c1dff..fba7f9b 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -25,6 +25,9 @@ #include #include #include +#include + +#include "tipwmss.h" /* EHRPWM registers and bits definitions */ @@ -107,6 +110,13 @@ #define AQCSFRC_CSFA_FRCHIGH BIT(1) #define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0)) +#define EPWMCLK_EN BIT(8) +#define EPWMCLK_STOP_REQ BIT(9) + +#define EPWMCLK_EN_ACK BIT(8) + +#define PWM_CELL_SIZE 3 + #define NUM_PWM_CHANNEL2 /* EHRPWM channels */ struct ehrpwm_pwm_chip { @@ -392,6 +402,16 @@ static const struct pwm_ops ehrpwm_pwm_ops = { .owner = THIS_MODULE, }; +#ifdef CONFIG_OF +static const struct of_device_id ehrpwm_of_match[] = { + { + .compatible = "ti,am33xx-ehrpwm", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, ehrpwm_of_match); +#endif + static int __devinit ehrpwm_pwm_probe(struct platform_device *pdev) { int ret; @@ -419,6 +439,7 @@ static int __devinit ehrpwm_pwm_probe(struct platform_device *pdev) pc->chip.dev = >dev; pc->chip.ops = _pwm_ops; + pc->chip.of_pwm_n_cells = PWM_CELL_SIZE; pc->chip.base = -1; pc->chip.npwm = NUM_PWM_CHANNEL; @@ -437,16 +458,38 @@ static int __devinit ehrpwm_pwm_probe(struct platform_device *pdev) dev_err(>dev, "pwmchip_add() failed: %d\n", ret); return ret; } - pm_runtime_enable(>dev); + pm_runtime_get_sync(>dev); + if (!(pwmss_submodule_state_change(pdev->dev.parent, EPWMCLK_EN) & + EPWMCLK_EN_ACK)) { + dev_err(>dev, "PWMSS config space clock enable failure\n"); + ret = -EINVAL; + goto pwmss_clk_failure; + } + pm_runtime_put_sync(>dev); + platform_set_drvdata(pdev, pc); return 0; + +pwmss_clk_failure: + pm_runtime_put_sync(>dev); + pm_runtime_disable(>dev); + pwmchip_remove(>chip); + return ret; } static int __devexit ehrpwm_pwm_remove(struct platform_device *pdev) { struct ehrpwm_pwm_chip *pc = platform_get_drvdata(pdev); + pm_runtime_get_sync(>dev); + /* +* Due to hardware misbehaviour, acknowledge of the stop_req +* is missing. Hence checking of the status bit skipped. +*/ + pwmss_submodule_state_change(pdev->dev.parent, EPWMCLK_STOP_REQ); + pm_runtime_put_sync(>dev); + pm_runtime_put_sync(>dev); pm_runtime_disable(>dev); return pwmchip_remove(>chip); @@ -454,7 +497,9 @@ static int __devexit ehrpwm_pwm_remove(struct platform_device *pdev) static struct platform_driver
[PATCH v2 06/10] pwm: pwm-tiehrpwm: Add device-tree binding support for EHRPWM driver
This patch 1. Add support for device-tree binding for EHRWPM driver. 2. Set size of pwm-cells set to 3 to support PWM channel number, PWM period polarity configuration from device tree. 3. Add enable/disable clock gating in PWM subsystem common config space. 4. When here set .owner member in platform_driver structure to THIS_MODULE. Signed-off-by: Philip, Avinash avinashphi...@ti.com Cc: Grant Likely grant.lik...@secretlab.ca Cc: Rob Herring rob.herr...@calxeda.com Cc: Rob Landley r...@landley.net --- Changes since v1: - Add separate patch for pinctrl support - Add conditional check for PWM subsystem clock enable. - Combined with HWMOD changes DT bindings. - Remove the custom of xlate support. :00 100644 000... aa2ed0a... A Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt :100644 100644 d3c1dff... fba7f9b... M drivers/pwm/pwm-tiehrpwm.c .../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 25 ++ drivers/pwm/pwm-tiehrpwm.c | 49 +++- 2 files changed, 72 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt new file mode 100644 index 000..aa2ed0a --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt @@ -0,0 +1,25 @@ +TI SOC EHRPWM based PWM controller + +Required properties: +- compatible : Must be ti,am33xx-ehrpwm +- #pwm-cells: Should be 3. Number of cells being used to specify PWM property. + First cell specifies the per-chip index of the PWM to use, the second + cell is the period cycle in nanoseconds and bit 0 in the third cell is + used to encode the polarity of PWM output. +- reg: physical base address and size of the registers map. + +Optional properties: +- ti,hwmods: Name of the hwmod associated to the EHRPWM: + ehrpwmx, x being the 0-based instance number from the HW spec +- tbclkgating: platforms require tbclk gating from control module + should populate + +Example: + +ehrpwm0: ehrpwm@0 { + compatible = ti,am33xx-ehrpwm; + #pwm-cells = 3; + reg = 0x48300200 0x100; + ti,hwmods = ehrpwm0; + tbclkgating; +}; diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index d3c1dff..fba7f9b 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -25,6 +25,9 @@ #include linux/err.h #include linux/clk.h #include linux/pm_runtime.h +#include linux/of_device.h + +#include tipwmss.h /* EHRPWM registers and bits definitions */ @@ -107,6 +110,13 @@ #define AQCSFRC_CSFA_FRCHIGH BIT(1) #define AQCSFRC_CSFA_DISSWFRC (BIT(1) | BIT(0)) +#define EPWMCLK_EN BIT(8) +#define EPWMCLK_STOP_REQ BIT(9) + +#define EPWMCLK_EN_ACK BIT(8) + +#define PWM_CELL_SIZE 3 + #define NUM_PWM_CHANNEL2 /* EHRPWM channels */ struct ehrpwm_pwm_chip { @@ -392,6 +402,16 @@ static const struct pwm_ops ehrpwm_pwm_ops = { .owner = THIS_MODULE, }; +#ifdef CONFIG_OF +static const struct of_device_id ehrpwm_of_match[] = { + { + .compatible = ti,am33xx-ehrpwm, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, ehrpwm_of_match); +#endif + static int __devinit ehrpwm_pwm_probe(struct platform_device *pdev) { int ret; @@ -419,6 +439,7 @@ static int __devinit ehrpwm_pwm_probe(struct platform_device *pdev) pc-chip.dev = pdev-dev; pc-chip.ops = ehrpwm_pwm_ops; + pc-chip.of_pwm_n_cells = PWM_CELL_SIZE; pc-chip.base = -1; pc-chip.npwm = NUM_PWM_CHANNEL; @@ -437,16 +458,38 @@ static int __devinit ehrpwm_pwm_probe(struct platform_device *pdev) dev_err(pdev-dev, pwmchip_add() failed: %d\n, ret); return ret; } - pm_runtime_enable(pdev-dev); + pm_runtime_get_sync(pdev-dev); + if (!(pwmss_submodule_state_change(pdev-dev.parent, EPWMCLK_EN) + EPWMCLK_EN_ACK)) { + dev_err(pdev-dev, PWMSS config space clock enable failure\n); + ret = -EINVAL; + goto pwmss_clk_failure; + } + pm_runtime_put_sync(pdev-dev); + platform_set_drvdata(pdev, pc); return 0; + +pwmss_clk_failure: + pm_runtime_put_sync(pdev-dev); + pm_runtime_disable(pdev-dev); + pwmchip_remove(pc-chip); + return ret; } static int __devexit ehrpwm_pwm_remove(struct platform_device *pdev) { struct ehrpwm_pwm_chip *pc = platform_get_drvdata(pdev); + pm_runtime_get_sync(pdev-dev); + /* +* Due to hardware misbehaviour, acknowledge of the stop_req +* is missing. Hence checking of the status bit skipped. +*/ + pwmss_submodule_state_change(pdev-dev.parent, EPWMCLK_STOP_REQ); + pm_runtime_put_sync(pdev-dev); + pm_runtime_put_sync(pdev-dev); pm_runtime_disable(pdev-dev);