From: Ondrej Jirman <meg...@megous.com>
PLL1 on H3 requires special factors application algorithm,
when the rate is changed. This algorithm was extracted
from the arisc code that handles frequency scaling
in the BSP kernel.
This algorithm is implemented by sun8i-h3-pll1-clk.
Signed-off-by: Ondrej Jirman <meg...@megous.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 4a4926b..b3247f4 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -106,7 +106,7 @@
pll1: clk@01c20000 {
#clock-cells = <0>;
- compatible = "allwinner,sun8i-a23-pll1-clk";
+ compatible = "allwinner,sun8i-h3-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
clock-output-names = "pll1";
--
2.9.0
