[PATCH v2 08/10] clk: sunxi-ng: support R40 SoC
From: Icenowy Zheng Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng --- Changes in v2: - Fixes according to the SoC's user manual. drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile |1 + drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1153 + drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++ include/dt-bindings/clock/sun8i-r40-ccu.h | 191 + include/dt-bindings/reset/sun8i-r40-ccu.h | 129 6 files changed, 1552 insertions(+) create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig index 64088e599404..e6884eafde44 100644 --- a/drivers/clk/sunxi-ng/Kconfig +++ b/drivers/clk/sunxi-ng/Kconfig @@ -140,6 +140,16 @@ config SUN8I_V3S_CCU default MACH_SUN8I depends on MACH_SUN8I || COMPILE_TEST +config SUN8I_R40_CCU + bool "Support for the Allwinner R40 CCU" + select SUNXI_CCU_DIV + select SUNXI_CCU_NK + select SUNXI_CCU_NKM + select SUNXI_CCU_NKMP + select SUNXI_CCU_NM + select SUNXI_CCU_MP + default MACH_SUN8I + config SUN9I_A80_CCU bool "Support for the Allwinner A80 CCU" select SUNXI_CCU_DIV diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile index 0ec02fe14c50..aa00b641484e 100644 --- a/drivers/clk/sunxi-ng/Makefile +++ b/drivers/clk/sunxi-ng/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o obj-$(CONFIG_SUN8I_V3S_CCU)+= ccu-sun8i-v3s.o obj-$(CONFIG_SUN8I_R_CCU) += ccu-sun8i-r.o +obj-$(CONFIG_SUN8I_R40_CCU)+= ccu-sun8i-r40.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-de.o obj-$(CONFIG_SUN9I_A80_CCU)+= ccu-sun9i-a80-usb.o diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c new file mode 100644 index ..0cc1b1ab7c3f --- /dev/null +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c @@ -0,0 +1,1153 @@ +/* + * Copyright (c) 2016 Icenowy Zheng + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +#include "ccu_common.h" +#include "ccu_reset.h" + +#include "ccu_div.h" +#include "ccu_gate.h" +#include "ccu_mp.h" +#include "ccu_mult.h" +#include "ccu_nk.h" +#include "ccu_nkm.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" +#include "ccu_phase.h" + +#include "ccu-sun8i-r40.h" + +static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", +"osc24M", 0x000, +8, 5, /* N */ +4, 2, /* K */ +0, 2, /* M */ +16, 2, /* P */ +BIT(31), /* gate */ +BIT(28), /* lock */ +0); + +/* + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from + * the base (2x, 4x and 8x), and one variable divider (the one true + * pll audio). + * + * We don't have any need for the variable divider for now, so we just + * hardcode it to match with the clock names + */ +#define SUN8I_R40_PLL_AUDIO_REG0x008 + +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", + "osc24M", 0x008, + 8, 7,/* N */ + 0, 5,/* M */ + BIT(31), /* gate */ + BIT(28), /* lock */ + 0); + +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", + "osc24M", 0x0010, + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24),/* frac enable */ + BIT(25),/* frac select */ + 27000, /* frac rate 0 */ + 29700, /* frac rate 1
Re: [PATCH v2 08/10] clk: sunxi-ng: support R40 SoC
On Thu, May 04, 2017 at 09:50:04PM +0800, Icenowy Zheng wrote: > From: Icenowy Zheng > > Allwinner R40 SoC have a clock controller module in the style of the > SoCs beyond sun6i, however, it's more rich and complex. > > Add support for it. > > Signed-off-by: Icenowy Zheng > --- > Changes in v2: > - Fixes according to the SoC's user manual. > > drivers/clk/sunxi-ng/Kconfig | 10 + > drivers/clk/sunxi-ng/Makefile |1 + > drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 1153 > + > drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 68 ++ > include/dt-bindings/clock/sun8i-r40-ccu.h | 191 + > include/dt-bindings/reset/sun8i-r40-ccu.h | 129 > 6 files changed, 1552 insertions(+) > create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.c > create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-r40.h > create mode 100644 include/dt-bindings/clock/sun8i-r40-ccu.h > create mode 100644 include/dt-bindings/reset/sun8i-r40-ccu.h > > diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig > index 64088e599404..e6884eafde44 100644 > --- a/drivers/clk/sunxi-ng/Kconfig > +++ b/drivers/clk/sunxi-ng/Kconfig > @@ -140,6 +140,16 @@ config SUN8I_V3S_CCU > default MACH_SUN8I > depends on MACH_SUN8I || COMPILE_TEST > > +config SUN8I_R40_CCU > + bool "Support for the Allwinner R40 CCU" > + select SUNXI_CCU_DIV > + select SUNXI_CCU_NK > + select SUNXI_CCU_NKM > + select SUNXI_CCU_NKMP > + select SUNXI_CCU_NM > + select SUNXI_CCU_MP > + default MACH_SUN8I > + > config SUN9I_A80_CCU > bool "Support for the Allwinner A80 CCU" > select SUNXI_CCU_DIV > diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile > index 0ec02fe14c50..aa00b641484e 100644 > --- a/drivers/clk/sunxi-ng/Makefile > +++ b/drivers/clk/sunxi-ng/Makefile > @@ -26,6 +26,7 @@ obj-$(CONFIG_SUN8I_A33_CCU) += ccu-sun8i-a33.o > obj-$(CONFIG_SUN8I_H3_CCU) += ccu-sun8i-h3.o > obj-$(CONFIG_SUN8I_V3S_CCU) += ccu-sun8i-v3s.o > obj-$(CONFIG_SUN8I_R_CCU)+= ccu-sun8i-r.o > +obj-$(CONFIG_SUN8I_R40_CCU) += ccu-sun8i-r40.o > obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80.o > obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-de.o > obj-$(CONFIG_SUN9I_A80_CCU) += ccu-sun9i-a80-usb.o > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c > b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c > new file mode 100644 > index ..0cc1b1ab7c3f > --- /dev/null > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c > @@ -0,0 +1,1153 @@ > +/* > + * Copyright (c) 2016 Icenowy Zheng > + * > + * This software is licensed under the terms of the GNU General Public > + * License version 2, as published by the Free Software Foundation, and > + * may be copied, distributed, and modified under those terms. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include > +#include > + > +#include "ccu_common.h" > +#include "ccu_reset.h" > + > +#include "ccu_div.h" > +#include "ccu_gate.h" > +#include "ccu_mp.h" > +#include "ccu_mult.h" > +#include "ccu_nk.h" > +#include "ccu_nkm.h" > +#include "ccu_nkmp.h" > +#include "ccu_nm.h" > +#include "ccu_phase.h" > + > +#include "ccu-sun8i-r40.h" > + > +static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", > + "osc24M", 0x000, > + 8, 5, /* N */ > + 4, 2, /* K */ > + 0, 2, /* M */ > + 16, 2, /* P */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + > +/* > + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from > + * the base (2x, 4x and 8x), and one variable divider (the one true > + * pll audio). > + * > + * We don't have any need for the variable divider for now, so we just > + * hardcode it to match with the clock names > + */ > +#define SUN8I_R40_PLL_AUDIO_REG 0x008 > + > +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", > +"osc24M", 0x008, > +8, 7,/* N */ > +0, 5,/* M */ > +BIT(31), /* gate */ > +BIT(28), /* lock */ > +0); > + > +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", > + "osc24M", 0x0010, > + 8, 7, /* N */ > + 0, 4, /* M */ > + BIT(24),
