Re: [PATCH v2 08/15] clock: milbeaut: Add Milbeaut M10V clock controller
Hi,
Thank you for your comments.
On 2019/02/23 8:57, Stephen Boyd wrote:
Quoting Sugaya Taichi (2019-02-08 04:27:17)
diff --git a/drivers/clk/clk-milbeaut.c b/drivers/clk/clk-milbeaut.c
new file mode 100644
index 000..f798939
--- /dev/null
+++ b/drivers/clk/clk-milbeaut.c
@@ -0,0 +1,626 @@
[]
+struct m10v_clk_div_fixed_data {
+ const char *name;
+ const char *parent_name;
+ u8 div;
+ u8 mult;
+ int onecell_idx;
+};
+struct m10v_clk_mux_factors {
+ const char *name;
+ const char * const *parent_names;
+ u8 num_parents;
+ u32 offset;
+ u8 shift;
+ u8 mask;
+ u32 *table;
+ unsigned long mux_flags;
+ int onecell_idx;
+};
Please add newlines between struct definitions. It also wouldn't hurt to
have kernel-doc on these.
I got it.
+
+static const struct clk_div_table emmcclk_table[] = {
+ { .val = 0, .div = 8 },
+ { .val = 1, .div = 9 },
+ { .val = 2, .div = 10 },
+ { .val = 3, .div = 15 },
+ { .div = 0 },
+};
+static const struct clk_div_table mclk400_table[] = {
+ { .val = 1, .div = 2 },
+ { .val = 3, .div = 4 },
+ { .div = 0 },
+};
+static const struct clk_div_table mclk200_table[] = {
+ { .val = 3, .div = 4 },
+ { .val = 7, .div = 8 },
+ { .div = 0 },
+};
+static const struct clk_div_table aclk400_table[] = {
+ { .val = 1, .div = 2 },
+ { .val = 3, .div = 4 },
+ { .div = 0 },
+};
+static const struct clk_div_table aclk300_table[] = {
+ { .val = 0, .div = 2 },
+ { .val = 1, .div = 3 },
+ { .div = 0 },
+};
+static const struct clk_div_table aclk_table[] = {
+ { .val = 3, .div = 4 },
+ { .val = 7, .div = 8 },
+ { .div = 0 },
+};
+static const struct clk_div_table aclkexs_table[] = {
+ { .val = 3, .div = 4 },
+ { .val = 4, .div = 5 },
+ { .val = 5, .div = 6 },
+ { .val = 7, .div = 8 },
+ { .div = 0 },
+};
+static const struct clk_div_table hclk_table[] = {
+ { .val = 7, .div = 8 },
+ { .val = 15, .div = 16 },
+ { .div = 0 },
+};
+static const struct clk_div_table hclkbmh_table[] = {
+ { .val = 3, .div = 4 },
+ { .val = 7, .div = 8 },
+ { .div = 0 },
+};
+static const struct clk_div_table pclk_table[] = {
+ { .val = 15, .div = 16 },
+ { .val = 31, .div = 32 },
+ { .div = 0 },
+};
+static const struct clk_div_table rclk_table[] = {
+ { .val = 0, .div = 8 },
+ { .val = 1, .div = 16 },
+ { .val = 2, .div = 24 },
+ { .val = 3, .div = 32 },
+ { .div = 0 },
+};
+static const struct clk_div_table uhs1clk0_table[] = {
+ { .val = 0, .div = 2 },
+ { .val = 1, .div = 3 },
+ { .val = 2, .div = 4 },
+ { .val = 3, .div = 8 },
+ { .val = 4, .div = 16 },
+ { .div = 0 },
+};
+static const struct clk_div_table uhs2clk_table[] = {
+ { .val = 0, .div = 9 },
+ { .val = 1, .div = 10 },
+ { .val = 2, .div = 11 },
+ { .val = 3, .div = 12 },
+ { .val = 4, .div = 13 },
+ { .val = 5, .div = 14 },
+ { .val = 6, .div = 16 },
+ { .val = 7, .div = 18 },
+ { .div = 0 },
+};
Same comment applies here. Newlines between tables please.
OK.
+
+static u32 spi_mux_table[] = {0, 1, 2};
+static const char * const spi_mux_names[] = {
+ M10V_SPI_PARENT0, M10V_SPI_PARENT1, M10V_SPI_PARENT2
+};
+
+static u32 uhs1clk2_mux_table[] = {2, 3, 4, 8};
+static const char * const uhs1clk2_mux_names[] = {
+ M10V_UHS1CLK2_PARENT0, M10V_UHS1CLK2_PARENT1,
+ M10V_UHS1CLK2_PARENT2, M10V_PLL6DIV2
+};
+
+static u32 uhs1clk1_mux_table[] = {3, 4, 8};
+static const char * const uhs1clk1_mux_names[] = {
+ M10V_UHS1CLK1_PARENT0, M10V_UHS1CLK1_PARENT1, M10V_PLL6DIV2
+};
+
[...]
+
+static const struct m10v_clk_mux_factors m10v_mux_factor_data[] = {
+ {"spi", spi_mux_names, ARRAY_SIZE(spi_mux_names),
+ CLKSEL(8), 3, 7, spi_mux_table, 0, M10V_SPICLK_ID},
+ {"uhs1clk2", uhs1clk2_mux_names, ARRAY_SIZE(uhs1clk2_mux_names),
+ CLKSEL(1), 13, 31, uhs1clk2_mux_table, 0, -1},
+ {"uhs1clk1", uhs1clk1_mux_names, ARRAY_SIZE(uhs1clk1_mux_names),
+ CLKSEL(1), 8, 31, uhs1clk1_mux_table, 0, -1},
+ {"nfclk", nfclk_mux_names, ARRAY_SIZE(nfclk_mux_names),
+ CLKSEL(1), 22, 127, nfclk_mux_table, 0, M10V_NFCLK_ID},
+};
+
+static u8 m10v_mux_get_parent(struct clk_hw *hw)
+{
+ struct clk_mux *mux = to_clk_mux(hw);
+ u32 val;
+
+ val = clk_readl(mux->reg) >> mux->shift;
Please don't use clk_readl() unless you absolutely need it.
OK, I try to use "readl()" simply.
+ val &= mux->mask;
+
+ return clk_mux_val_to_index(hw, mux->table, mux->flags,
Re: [PATCH v2 08/15] clock: milbeaut: Add Milbeaut M10V clock controller
Quoting Sugaya Taichi (2019-02-08 04:27:17)
> diff --git a/drivers/clk/clk-milbeaut.c b/drivers/clk/clk-milbeaut.c
> new file mode 100644
> index 000..f798939
> --- /dev/null
> +++ b/drivers/clk/clk-milbeaut.c
> @@ -0,0 +1,626 @@
[]
> +struct m10v_clk_div_fixed_data {
> + const char *name;
> + const char *parent_name;
> + u8 div;
> + u8 mult;
> + int onecell_idx;
> +};
> +struct m10v_clk_mux_factors {
> + const char *name;
> + const char * const *parent_names;
> + u8 num_parents;
> + u32 offset;
> + u8 shift;
> + u8 mask;
> + u32 *table;
> + unsigned long mux_flags;
> + int onecell_idx;
> +};
Please add newlines between struct definitions. It also wouldn't hurt to
have kernel-doc on these.
> +
> +static const struct clk_div_table emmcclk_table[] = {
> + { .val = 0, .div = 8 },
> + { .val = 1, .div = 9 },
> + { .val = 2, .div = 10 },
> + { .val = 3, .div = 15 },
> + { .div = 0 },
> +};
> +static const struct clk_div_table mclk400_table[] = {
> + { .val = 1, .div = 2 },
> + { .val = 3, .div = 4 },
> + { .div = 0 },
> +};
> +static const struct clk_div_table mclk200_table[] = {
> + { .val = 3, .div = 4 },
> + { .val = 7, .div = 8 },
> + { .div = 0 },
> +};
> +static const struct clk_div_table aclk400_table[] = {
> + { .val = 1, .div = 2 },
> + { .val = 3, .div = 4 },
> + { .div = 0 },
> +};
> +static const struct clk_div_table aclk300_table[] = {
> + { .val = 0, .div = 2 },
> + { .val = 1, .div = 3 },
> + { .div = 0 },
> +};
> +static const struct clk_div_table aclk_table[] = {
> + { .val = 3, .div = 4 },
> + { .val = 7, .div = 8 },
> + { .div = 0 },
> +};
> +static const struct clk_div_table aclkexs_table[] = {
> + { .val = 3, .div = 4 },
> + { .val = 4, .div = 5 },
> + { .val = 5, .div = 6 },
> + { .val = 7, .div = 8 },
> + { .div = 0 },
> +};
> +static const struct clk_div_table hclk_table[] = {
> + { .val = 7, .div = 8 },
> + { .val = 15, .div = 16 },
> + { .div = 0 },
> +};
> +static const struct clk_div_table hclkbmh_table[] = {
> + { .val = 3, .div = 4 },
> + { .val = 7, .div = 8 },
> + { .div = 0 },
> +};
> +static const struct clk_div_table pclk_table[] = {
> + { .val = 15, .div = 16 },
> + { .val = 31, .div = 32 },
> + { .div = 0 },
> +};
> +static const struct clk_div_table rclk_table[] = {
> + { .val = 0, .div = 8 },
> + { .val = 1, .div = 16 },
> + { .val = 2, .div = 24 },
> + { .val = 3, .div = 32 },
> + { .div = 0 },
> +};
> +static const struct clk_div_table uhs1clk0_table[] = {
> + { .val = 0, .div = 2 },
> + { .val = 1, .div = 3 },
> + { .val = 2, .div = 4 },
> + { .val = 3, .div = 8 },
> + { .val = 4, .div = 16 },
> + { .div = 0 },
> +};
> +static const struct clk_div_table uhs2clk_table[] = {
> + { .val = 0, .div = 9 },
> + { .val = 1, .div = 10 },
> + { .val = 2, .div = 11 },
> + { .val = 3, .div = 12 },
> + { .val = 4, .div = 13 },
> + { .val = 5, .div = 14 },
> + { .val = 6, .div = 16 },
> + { .val = 7, .div = 18 },
> + { .div = 0 },
> +};
Same comment applies here. Newlines between tables please.
> +
> +static u32 spi_mux_table[] = {0, 1, 2};
> +static const char * const spi_mux_names[] = {
> + M10V_SPI_PARENT0, M10V_SPI_PARENT1, M10V_SPI_PARENT2
> +};
> +
> +static u32 uhs1clk2_mux_table[] = {2, 3, 4, 8};
> +static const char * const uhs1clk2_mux_names[] = {
> + M10V_UHS1CLK2_PARENT0, M10V_UHS1CLK2_PARENT1,
> + M10V_UHS1CLK2_PARENT2, M10V_PLL6DIV2
> +};
> +
> +static u32 uhs1clk1_mux_table[] = {3, 4, 8};
> +static const char * const uhs1clk1_mux_names[] = {
> + M10V_UHS1CLK1_PARENT0, M10V_UHS1CLK1_PARENT1, M10V_PLL6DIV2
> +};
> +
[...]
> +
> +static const struct m10v_clk_mux_factors m10v_mux_factor_data[] = {
> + {"spi", spi_mux_names, ARRAY_SIZE(spi_mux_names),
> + CLKSEL(8), 3, 7, spi_mux_table, 0, M10V_SPICLK_ID},
> + {"uhs1clk2", uhs1clk2_mux_names, ARRAY_SIZE(uhs1clk2_mux_names),
> + CLKSEL(1), 13, 31, uhs1clk2_mux_table, 0, -1},
> + {"uhs1clk1", uhs1clk1_mux_names, ARRAY_SIZE(uhs1clk1_mux_names),
> + CLKSEL(1), 8, 31, uhs1clk1_mux_table, 0, -1},
> + {"nfclk", nfclk_mux_names, ARRAY_SIZE(nfclk_mux_names),
> + CLKSEL(1), 22, 127, nfclk_mux_table, 0, M10V_NFCLK_ID},
> +};
> +
> +static u8 m10v_mux_get_parent(struct clk_hw *hw)
> +{
> + struct clk_mux *mux = to_clk_mux(hw);
> + u32 val;
> +
> + val = clk_readl(mux->reg) >> mux->shift;
Please don't use
[PATCH v2 08/15] clock: milbeaut: Add Milbeaut M10V clock controller
The M10V of the Milbeaut SoCs has an on-chip controller that derive
mostly clocks from a single external clock, using PLLs, dividers,
multiplexers and gates. Since the PLLs have already been started and
will not stop / restart, they are fixed factor. Gates will be added in
later patch (all gates are off state).
Signed-off-by: Sugaya Taichi
---
drivers/clk/Makefile | 1 +
drivers/clk/clk-milbeaut.c | 626 +
2 files changed, 627 insertions(+)
create mode 100644 drivers/clk/clk-milbeaut.c
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 8a9440a..84a78e8 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
obj-$(CONFIG_COMMON_CLK_ASPEED)+= clk-aspeed.o
obj-$(CONFIG_ARCH_HIGHBANK)+= clk-highbank.o
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
+obj-$(CONFIG_ARCH_MILBEAUT_M10V) += clk-milbeaut.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
obj-$(CONFIG_COMMON_CLK_MAX9485) += clk-max9485.o
obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
diff --git a/drivers/clk/clk-milbeaut.c b/drivers/clk/clk-milbeaut.c
new file mode 100644
index 000..f798939
--- /dev/null
+++ b/drivers/clk/clk-milbeaut.c
@@ -0,0 +1,626 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Socionext Inc.
+ * Copyright (C) 2016 Linaro Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define M10V_CLKSEL1 0x0
+#define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1)
+
+#define M10V_PLL1 "pll1"
+#define M10V_PLL1DIV2 "pll1-2"
+#define M10V_PLL2 "pll2"
+#define M10V_PLL2DIV2 "pll2-2"
+#define M10V_PLL6 "pll6"
+#define M10V_PLL6DIV2 "pll6-2"
+#define M10V_PLL6DIV3 "pll6-3"
+#define M10V_PLL7 "pll7"
+#define M10V_PLL7DIV2 "pll7-2"
+#define M10V_PLL7DIV5 "pll7-5"
+#define M10V_PLL9 "pll9"
+#define M10V_PLL10 "pll10"
+#define M10V_PLL10DIV2 "pll10-2"
+#define M10V_PLL11 "pll11"
+
+#define M10V_SPI_PARENT0 "spi-parent0"
+#define M10V_SPI_PARENT1 "spi-parent1"
+#define M10V_SPI_PARENT2 "spi-parent2"
+#define M10V_UHS1CLK2_PARENT0 "uhs1clk2-parent0"
+#define M10V_UHS1CLK2_PARENT1 "uhs1clk2-parent1"
+#define M10V_UHS1CLK2_PARENT2 "uhs1clk2-parent2"
+#define M10V_UHS1CLK1_PARENT0 "uhs1clk1-parent0"
+#define M10V_UHS1CLK1_PARENT1 "uhs1clk1-parent1"
+#define M10V_NFCLK_PARENT0 "nfclk-parent0"
+#define M10V_NFCLK_PARENT1 "nfclk-parent1"
+#define M10V_NFCLK_PARENT2 "nfclk-parent2"
+#define M10V_NFCLK_PARENT3 "nfclk-parent3"
+#define M10V_NFCLK_PARENT4 "nfclk-parent4"
+#define M10V_NFCLK_PARENT5 "nfclk-parent5"
+
+#define M10V_DCHREQ1
+#define M10V_UPOLL_RATE1
+#define M10V_UTIMEOUT 250
+
+#define M10V_EMMCCLK_ID0
+#define M10V_ACLK_ID 1
+#define M10V_HCLK_ID 2
+#define M10V_PCLK_ID 3
+#define M10V_RCLK_ID 4
+#define M10V_SPICLK_ID 5
+#define M10V_NFCLK_ID 6
+#define M10V_NUM_CLKS 7
+
+#define to_m10v_div(_hw)container_of(_hw, struct m10v_clk_divider, hw)
+
+static struct clk_hw_onecell_data *m10v_clk_data;
+
+static DEFINE_SPINLOCK(m10v_crglock);
+
+struct m10v_clk_pll_factors {
+ const char *name;
+ const char *parent_name;
+ u32 div;
+ u32 mult;
+};
+struct m10v_clk_div_factors {
+ const char *name;
+ const char *parent_name;
+ u32 offset;
+ u8 shift;
+ u8 width;
+ const struct clk_div_table *table;
+ unsigned long div_flags;
+ int onecell_idx;
+};
+struct m10v_clk_div_fixed_data {
+ const char *name;
+ const char *parent_name;
+ u8 div;
+ u8 mult;
+ int onecell_idx;
+};
+struct m10v_clk_mux_factors {
+ const char *name;
+ const char * const *parent_names;
+ u8 num_parents;
+ u32 offset;
+ u8 shift;
+ u8 mask;
+ u32 *table;
+ unsigned long mux_flags;
+ int onecell_idx;
+};
+
+static const struct clk_div_table emmcclk_table[] = {
+ { .val = 0, .div = 8 },
+ { .val = 1, .div = 9 },
+ { .val = 2, .div = 10 },
+ { .val = 3, .div = 15 },
+ { .div = 0 },
+};
+static const struct clk_div_table mclk400_table[] = {
+ { .val = 1, .div = 2 },
+ {
