Re: [PATCH v2 1/3] Documentation: dtb: xgene: Add PMD clock binding

[Hoan Tran]

On Mon, Sep 12, 2016 at 8:37 AM, Rob Herring  wrote:
> On Fri, Sep 02, 2016 at 05:40:53PM -0700, Hoan Tran wrote:
>> Add APM X-Gene clock binding documentation for PMD clock.
>>
>> Signed-off-by: Hoan Tran 
>> ---
>>  Documentation/devicetree/bindings/clock/xgene.txt | 18 ++
>>  1 file changed, 18 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/xgene.txt 
>> b/Documentation/devicetree/bindings/clock/xgene.txt
>> index 82f9638..e6e12ae 100644
>> --- a/Documentation/devicetree/bindings/clock/xgene.txt
>> +++ b/Documentation/devicetree/bindings/clock/xgene.txt
>> @@ -8,6 +8,7 @@ Required properties:
>>  - compatible : shall be one of the following:
>>   "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
>>   "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
>> + "apm,xgene-pmd-clock" - for a X-Gene PMD clock
>>   "apm,xgene-device-clock" - for a X-Gene device clock
>>   "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
>>   "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
>> @@ -22,6 +23,15 @@ Required properties for SoC or PCP PLL clocks:
>>  Optional properties for PLL clocks:
>>  - clock-names : shall be the name of the PLL. If missing, use the device 
>> name.
>>
>> +Required properties for PMD clocks:
>> +- reg : shall be the physical register address for the pmd clock.
>> +- clocks : shall be the input parent clock phandle for the clock.
>> +- #clock-cells : shall be set to 1.
>> +- clock-output-names : shall be the name of the clock referenced by derive
>> +  clock.
>> +Optional properties for PLL clocks:
>> +- clock-names : shall be the name of the clock. If missing, use the device 
>> name.
>> +
>>  Required properties for device clocks:
>>  - reg : shall be a list of address and length pairs describing the CSR
>>   reset and/or the divider. Either may be omitted, but at least
>> @@ -59,6 +69,14 @@ For example:
>>   type = <0>;
>>   };
>>
>> + pmd0clk: pmd0clk {
>
> Needs a unit address.
>
>> + compatible = "apm,xgene-pmd-clock";
>> + #clock-cells = <1>;
>> + clocks = < 0>;
>> + reg = <0x0 0x7E200200 0x0 0x10>;
>
> Lowercase hex please.
>
> With those,
>
> Acked-by: Rob Herring 

Thanks, Rob ! I'll send another version soon.

Regards
Hoan

>
>
>> + clock-output-names = "pmd0clk";
>> + };
>> +
>>   socpll: socpll@17000120 {
>>   compatible = "apm,xgene-socpll-clock";
>>   #clock-cells = <1>;
>> --
>> 1.9.1
>>

Re: [PATCH v2 1/3] Documentation: dtb: xgene: Add PMD clock binding

[Hoan Tran]

On Mon, Sep 12, 2016 at 8:37 AM, Rob Herring  wrote:
> On Fri, Sep 02, 2016 at 05:40:53PM -0700, Hoan Tran wrote:
>> Add APM X-Gene clock binding documentation for PMD clock.
>>
>> Signed-off-by: Hoan Tran 
>> ---
>>  Documentation/devicetree/bindings/clock/xgene.txt | 18 ++
>>  1 file changed, 18 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/xgene.txt 
>> b/Documentation/devicetree/bindings/clock/xgene.txt
>> index 82f9638..e6e12ae 100644
>> --- a/Documentation/devicetree/bindings/clock/xgene.txt
>> +++ b/Documentation/devicetree/bindings/clock/xgene.txt
>> @@ -8,6 +8,7 @@ Required properties:
>>  - compatible : shall be one of the following:
>>   "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
>>   "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
>> + "apm,xgene-pmd-clock" - for a X-Gene PMD clock
>>   "apm,xgene-device-clock" - for a X-Gene device clock
>>   "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
>>   "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
>> @@ -22,6 +23,15 @@ Required properties for SoC or PCP PLL clocks:
>>  Optional properties for PLL clocks:
>>  - clock-names : shall be the name of the PLL. If missing, use the device 
>> name.
>>
>> +Required properties for PMD clocks:
>> +- reg : shall be the physical register address for the pmd clock.
>> +- clocks : shall be the input parent clock phandle for the clock.
>> +- #clock-cells : shall be set to 1.
>> +- clock-output-names : shall be the name of the clock referenced by derive
>> +  clock.
>> +Optional properties for PLL clocks:
>> +- clock-names : shall be the name of the clock. If missing, use the device 
>> name.
>> +
>>  Required properties for device clocks:
>>  - reg : shall be a list of address and length pairs describing the CSR
>>   reset and/or the divider. Either may be omitted, but at least
>> @@ -59,6 +69,14 @@ For example:
>>   type = <0>;
>>   };
>>
>> + pmd0clk: pmd0clk {
>
> Needs a unit address.
>
>> + compatible = "apm,xgene-pmd-clock";
>> + #clock-cells = <1>;
>> + clocks = < 0>;
>> + reg = <0x0 0x7E200200 0x0 0x10>;
>
> Lowercase hex please.
>
> With those,
>
> Acked-by: Rob Herring 

Thanks, Rob ! I'll send another version soon.

Regards
Hoan

>
>
>> + clock-output-names = "pmd0clk";
>> + };
>> +
>>   socpll: socpll@17000120 {
>>   compatible = "apm,xgene-socpll-clock";
>>   #clock-cells = <1>;
>> --
>> 1.9.1
>>

Re: [PATCH v2 1/3] Documentation: dtb: xgene: Add PMD clock binding

[Rob Herring]

On Fri, Sep 02, 2016 at 05:40:53PM -0700, Hoan Tran wrote:
> Add APM X-Gene clock binding documentation for PMD clock.
> 
> Signed-off-by: Hoan Tran 
> ---
>  Documentation/devicetree/bindings/clock/xgene.txt | 18 ++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/xgene.txt 
> b/Documentation/devicetree/bindings/clock/xgene.txt
> index 82f9638..e6e12ae 100644
> --- a/Documentation/devicetree/bindings/clock/xgene.txt
> +++ b/Documentation/devicetree/bindings/clock/xgene.txt
> @@ -8,6 +8,7 @@ Required properties:
>  - compatible : shall be one of the following:
>   "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
>   "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
> + "apm,xgene-pmd-clock" - for a X-Gene PMD clock
>   "apm,xgene-device-clock" - for a X-Gene device clock
>   "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
>   "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
> @@ -22,6 +23,15 @@ Required properties for SoC or PCP PLL clocks:
>  Optional properties for PLL clocks:
>  - clock-names : shall be the name of the PLL. If missing, use the device 
> name.
>  
> +Required properties for PMD clocks:
> +- reg : shall be the physical register address for the pmd clock.
> +- clocks : shall be the input parent clock phandle for the clock.
> +- #clock-cells : shall be set to 1.
> +- clock-output-names : shall be the name of the clock referenced by derive
> +  clock.
> +Optional properties for PLL clocks:
> +- clock-names : shall be the name of the clock. If missing, use the device 
> name.
> +
>  Required properties for device clocks:
>  - reg : shall be a list of address and length pairs describing the CSR
>   reset and/or the divider. Either may be omitted, but at least
> @@ -59,6 +69,14 @@ For example:
>   type = <0>;
>   };
>  
> + pmd0clk: pmd0clk {

Needs a unit address.

> + compatible = "apm,xgene-pmd-clock";
> + #clock-cells = <1>;
> + clocks = < 0>;
> + reg = <0x0 0x7E200200 0x0 0x10>;

Lowercase hex please.

With those,

Acked-by: Rob Herring 


> + clock-output-names = "pmd0clk";
> + };
> +
>   socpll: socpll@17000120 {
>   compatible = "apm,xgene-socpll-clock";
>   #clock-cells = <1>;
> -- 
> 1.9.1
> 

Re: [PATCH v2 1/3] Documentation: dtb: xgene: Add PMD clock binding

[Rob Herring]

On Fri, Sep 02, 2016 at 05:40:53PM -0700, Hoan Tran wrote:
> Add APM X-Gene clock binding documentation for PMD clock.
> 
> Signed-off-by: Hoan Tran 
> ---
>  Documentation/devicetree/bindings/clock/xgene.txt | 18 ++
>  1 file changed, 18 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/clock/xgene.txt 
> b/Documentation/devicetree/bindings/clock/xgene.txt
> index 82f9638..e6e12ae 100644
> --- a/Documentation/devicetree/bindings/clock/xgene.txt
> +++ b/Documentation/devicetree/bindings/clock/xgene.txt
> @@ -8,6 +8,7 @@ Required properties:
>  - compatible : shall be one of the following:
>   "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
>   "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
> + "apm,xgene-pmd-clock" - for a X-Gene PMD clock
>   "apm,xgene-device-clock" - for a X-Gene device clock
>   "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
>   "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
> @@ -22,6 +23,15 @@ Required properties for SoC or PCP PLL clocks:
>  Optional properties for PLL clocks:
>  - clock-names : shall be the name of the PLL. If missing, use the device 
> name.
>  
> +Required properties for PMD clocks:
> +- reg : shall be the physical register address for the pmd clock.
> +- clocks : shall be the input parent clock phandle for the clock.
> +- #clock-cells : shall be set to 1.
> +- clock-output-names : shall be the name of the clock referenced by derive
> +  clock.
> +Optional properties for PLL clocks:
> +- clock-names : shall be the name of the clock. If missing, use the device 
> name.
> +
>  Required properties for device clocks:
>  - reg : shall be a list of address and length pairs describing the CSR
>   reset and/or the divider. Either may be omitted, but at least
> @@ -59,6 +69,14 @@ For example:
>   type = <0>;
>   };
>  
> + pmd0clk: pmd0clk {

Needs a unit address.

> + compatible = "apm,xgene-pmd-clock";
> + #clock-cells = <1>;
> + clocks = < 0>;
> + reg = <0x0 0x7E200200 0x0 0x10>;

Lowercase hex please.

With those,

Acked-by: Rob Herring 


> + clock-output-names = "pmd0clk";
> + };
> +
>   socpll: socpll@17000120 {
>   compatible = "apm,xgene-socpll-clock";
>   #clock-cells = <1>;
> -- 
> 1.9.1
> 

[PATCH v2 1/3] Documentation: dtb: xgene: Add PMD clock binding

[Hoan Tran]

Add APM X-Gene clock binding documentation for PMD clock.

Signed-off-by: Hoan Tran 
---
 Documentation/devicetree/bindings/clock/xgene.txt | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/xgene.txt 
b/Documentation/devicetree/bindings/clock/xgene.txt
index 82f9638..e6e12ae 100644
--- a/Documentation/devicetree/bindings/clock/xgene.txt
+++ b/Documentation/devicetree/bindings/clock/xgene.txt
@@ -8,6 +8,7 @@ Required properties:
 - compatible : shall be one of the following:
"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
+   "apm,xgene-pmd-clock" - for a X-Gene PMD clock
"apm,xgene-device-clock" - for a X-Gene device clock
"apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
"apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
@@ -22,6 +23,15 @@ Required properties for SoC or PCP PLL clocks:
 Optional properties for PLL clocks:
 - clock-names : shall be the name of the PLL. If missing, use the device name.
 
+Required properties for PMD clocks:
+- reg : shall be the physical register address for the pmd clock.
+- clocks : shall be the input parent clock phandle for the clock.
+- #clock-cells : shall be set to 1.
+- clock-output-names : shall be the name of the clock referenced by derive
+  clock.
+Optional properties for PLL clocks:
+- clock-names : shall be the name of the clock. If missing, use the device 
name.
+
 Required properties for device clocks:
 - reg : shall be a list of address and length pairs describing the CSR
  reset and/or the divider. Either may be omitted, but at least
@@ -59,6 +69,14 @@ For example:
type = <0>;
};
 
+   pmd0clk: pmd0clk {
+   compatible = "apm,xgene-pmd-clock";
+   #clock-cells = <1>;
+   clocks = < 0>;
+   reg = <0x0 0x7E200200 0x0 0x10>;
+   clock-output-names = "pmd0clk";
+   };
+
socpll: socpll@17000120 {
compatible = "apm,xgene-socpll-clock";
#clock-cells = <1>;
-- 
1.9.1

[PATCH v2 1/3] Documentation: dtb: xgene: Add PMD clock binding

[Hoan Tran]

Add APM X-Gene clock binding documentation for PMD clock.

Signed-off-by: Hoan Tran 
---
 Documentation/devicetree/bindings/clock/xgene.txt | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/xgene.txt 
b/Documentation/devicetree/bindings/clock/xgene.txt
index 82f9638..e6e12ae 100644
--- a/Documentation/devicetree/bindings/clock/xgene.txt
+++ b/Documentation/devicetree/bindings/clock/xgene.txt
@@ -8,6 +8,7 @@ Required properties:
 - compatible : shall be one of the following:
"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
+   "apm,xgene-pmd-clock" - for a X-Gene PMD clock
"apm,xgene-device-clock" - for a X-Gene device clock
"apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
"apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
@@ -22,6 +23,15 @@ Required properties for SoC or PCP PLL clocks:
 Optional properties for PLL clocks:
 - clock-names : shall be the name of the PLL. If missing, use the device name.
 
+Required properties for PMD clocks:
+- reg : shall be the physical register address for the pmd clock.
+- clocks : shall be the input parent clock phandle for the clock.
+- #clock-cells : shall be set to 1.
+- clock-output-names : shall be the name of the clock referenced by derive
+  clock.
+Optional properties for PLL clocks:
+- clock-names : shall be the name of the clock. If missing, use the device 
name.
+
 Required properties for device clocks:
 - reg : shall be a list of address and length pairs describing the CSR
  reset and/or the divider. Either may be omitted, but at least
@@ -59,6 +69,14 @@ For example:
type = <0>;
};
 
+   pmd0clk: pmd0clk {
+   compatible = "apm,xgene-pmd-clock";
+   #clock-cells = <1>;
+   clocks = < 0>;
+   reg = <0x0 0x7E200200 0x0 0x10>;
+   clock-output-names = "pmd0clk";
+   };
+
socpll: socpll@17000120 {
compatible = "apm,xgene-socpll-clock";
#clock-cells = <1>;
-- 
1.9.1