Re: [PATCH v2 1/3] dt-bindings: clock: meson: add A1 clock controller bindings
Hi, Jerome
Thanks for your review.
On 2019/10/21 18:43, Jerome Brunet wrote:
On Fri 18 Oct 2019 at 09:14, Jian Hu wrote:
Add the documentation to support Amlogic A1 clock driver,
and add A1 clock controller bindings.
Signed-off-by: Jian Hu
---
.../devicetree/bindings/clock/amlogic,a1-clkc.yaml | 143
+
Those are 2 different controllers, not variants.
One description (one file) per controller please
OK, I will describe for periphs and PLLs controller separately.
include/dt-bindings/clock/a1-clkc.h| 98 ++
include/dt-bindings/clock/a1-pll-clkc.h| 16 +++
3 files changed, 257 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
create mode 100644 include/dt-bindings/clock/a1-clkc.h
create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
new file mode 100644
index 000..b382eebe
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Amlogic Meson A/C serials Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Neil Armstrong
+ - Jerome Brunet
+ - Jian Hu
+
+description: |+
+ The clock controller node should be the child of a syscon node with the
+ required property:
+
+ - compatible: Should be one of the following:
+"amlogic,meson-a-analog-sysctrl", "syscon",
"simple-mfd"
+"amlogic,meson-a-periphs-sysctrl", "syscon",
"simple-mfd"
+
+ Refer to the the bindings described in
+ Documentation/devicetree/bindings/mfd/syscon.txt
+
+properties:
+ "#clock-cells":
+const: 1
+ compatible:
+- enum:
+- amlogic,a1-periphs-clkc
+- amlogic,a1-pll-clkc
+
+ reg:
+maxItems: 1
+
+ clocks:
+minItems: 2
+maxItems: 6
+
+ clock-names:
+minItems: 2
+maxItems: 6
+
+required:
+ - "#clock-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+if:
+ properties:
+compatible:
+ enum:
+- amlogic,a1-periphs-clkc
+
+then:
+ properties:
+clocks:
+ minItems: 2
+ maxItems: 2
+items:
+ - description: fixed pll gate clock
+ - description: hifi pll gate clock
+
+clock-names:
+ minItems: 2
+ maxItems: 2
+ items:
+- const: xtal_fixpll
+- const: xtal_hifipll
+
+else:
+ if:
+properties:
+ compatible:
+const: amlogic,a1-pll-clkc
+
+ then:
+properties:
+ clocks:
+minItems: 6
+maxItems: 6
+items:
+ - description: Input fixed pll div2
+ - description: Input fixed pll div3
+ - description: Input fixed pll div5
+ - description: Input fixed pll div7
+ - description: Periph Hifi pll
+ - description: Input Oscillator (usually at 24MHz)
+
+ clock-names:
+minItems: 6
+maxItems: 6
+items:
+ - const: fclk_div2
+ - const: fclk_div3
+ - const: fclk_div5
+ - const: fclk_div7
+ - const: hifi_pll
+ - const: xtal
+
+
+additionalProperties: false
+
+examples:
+ - |
+analog: system-controller@0 {
+compatible = "amlogic,meson-a-analog-sysctrl",
+ "simple-mfd", "syscon";
+reg = <0 0x7c00 0 0x21c>;
+
+clkc_pll: pll-clock-controller {
+compatible = "amlogic,a1-pll-clkc";
+#clock-cells = <1>;
+clocks = <_periphs CLKID_XTAL_FIXPLL>,
+ <_periphs CLKID_XTAL_HIFIPLL>;
+clock-names = "xtal_fixpll", "xtal_hifipll";
+};
+};
+
+ - |
+periphs: system-controller@1 {
+compatible = "amlogic,meson-a-periphs-sysctrl",
+ "simple-mfd", "syscon";
+reg = <0 0x800 0 0x104>;
+
+clkc_periphs: periphs-clock-controller {
+compatible = "amlogic,a1-periphs-clkc";
+#clock-cells = <1>;
+clocks = <_pll CLKID_FCLK_DIV2>,
+<_pll CLKID_FCLK_DIV3>,
+<_pll CLKID_FCLK_DIV5>,
+<_pll CLKID_FCLK_DIV7>,
+<_pll CLKID_HIFI_PLL>,
+<>;
+clock-names = "fclk_div2", "fclk_div3", "fclk_div5",
+ "fclk_div7", "hifi_pll", "xtal";
+};
+};
diff --git a/include/dt-bindings/clock/a1-clkc.h
b/include/dt-bindings/clock/a1-clkc.h
new file mode 100644
index 000..1ba0112
--- /dev/null
+++ b/include/dt-bindings/clock/a1-clkc.h
@@ -0,0 +1,98 @@
+/*
Re: [PATCH v2 1/3] dt-bindings: clock: meson: add A1 clock controller bindings
On Fri 18 Oct 2019 at 09:14, Jian Hu wrote:
> Add the documentation to support Amlogic A1 clock driver,
> and add A1 clock controller bindings.
>
> Signed-off-by: Jian Hu
> ---
> .../devicetree/bindings/clock/amlogic,a1-clkc.yaml | 143
> +
Those are 2 different controllers, not variants.
One description (one file) per controller please
> include/dt-bindings/clock/a1-clkc.h| 98 ++
> include/dt-bindings/clock/a1-pll-clkc.h| 16 +++
> 3 files changed, 257 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> create mode 100644 include/dt-bindings/clock/a1-clkc.h
> create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> new file mode 100644
> index 000..b382eebe
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
> @@ -0,0 +1,143 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> + */
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#;
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#;
> +
> +title: Amlogic Meson A/C serials Clock Control Unit Device Tree Bindings
> +
> +maintainers:
> + - Neil Armstrong
> + - Jerome Brunet
> + - Jian Hu
> +
> +description: |+
> + The clock controller node should be the child of a syscon node with the
> + required property:
> +
> + - compatible: Should be one of the following:
> +"amlogic,meson-a-analog-sysctrl", "syscon",
> "simple-mfd"
> +"amlogic,meson-a-periphs-sysctrl", "syscon",
> "simple-mfd"
> +
> + Refer to the the bindings described in
> + Documentation/devicetree/bindings/mfd/syscon.txt
> +
> +properties:
> + "#clock-cells":
> +const: 1
> + compatible:
> +- enum:
> +- amlogic,a1-periphs-clkc
> +- amlogic,a1-pll-clkc
> +
> + reg:
> +maxItems: 1
> +
> + clocks:
> +minItems: 2
> +maxItems: 6
> +
> + clock-names:
> +minItems: 2
> +maxItems: 6
> +
> +required:
> + - "#clock-cells"
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +if:
> + properties:
> +compatible:
> + enum:
> +- amlogic,a1-periphs-clkc
> +
> +then:
> + properties:
> +clocks:
> + minItems: 2
> + maxItems: 2
> +items:
> + - description: fixed pll gate clock
> + - description: hifi pll gate clock
> +
> +clock-names:
> + minItems: 2
> + maxItems: 2
> + items:
> +- const: xtal_fixpll
> +- const: xtal_hifipll
> +
> +else:
> + if:
> +properties:
> + compatible:
> +const: amlogic,a1-pll-clkc
> +
> + then:
> +properties:
> + clocks:
> +minItems: 6
> +maxItems: 6
> +items:
> + - description: Input fixed pll div2
> + - description: Input fixed pll div3
> + - description: Input fixed pll div5
> + - description: Input fixed pll div7
> + - description: Periph Hifi pll
> + - description: Input Oscillator (usually at 24MHz)
> +
> + clock-names:
> +minItems: 6
> +maxItems: 6
> +items:
> + - const: fclk_div2
> + - const: fclk_div3
> + - const: fclk_div5
> + - const: fclk_div7
> + - const: hifi_pll
> + - const: xtal
> +
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +analog: system-controller@0 {
> +compatible = "amlogic,meson-a-analog-sysctrl",
> + "simple-mfd", "syscon";
> +reg = <0 0x7c00 0 0x21c>;
> +
> +clkc_pll: pll-clock-controller {
> +compatible = "amlogic,a1-pll-clkc";
> +#clock-cells = <1>;
> +clocks = <_periphs CLKID_XTAL_FIXPLL>,
> + <_periphs CLKID_XTAL_HIFIPLL>;
> +clock-names = "xtal_fixpll", "xtal_hifipll";
> +};
> +};
> +
> + - |
> +periphs: system-controller@1 {
> +compatible = "amlogic,meson-a-periphs-sysctrl",
> + "simple-mfd", "syscon";
> +reg = <0 0x800 0 0x104>;
> +
> +clkc_periphs: periphs-clock-controller {
> +compatible = "amlogic,a1-periphs-clkc";
> +#clock-cells = <1>;
> +clocks = <_pll CLKID_FCLK_DIV2>,
> +<_pll CLKID_FCLK_DIV3>,
> +<_pll CLKID_FCLK_DIV5>,
> +<_pll CLKID_FCLK_DIV7>,
> +<_pll CLKID_HIFI_PLL>,
> +<>;
> +clock-names = "fclk_div2", "fclk_div3", "fclk_div5",
> + "fclk_div7", "hifi_pll", "xtal";
> +};
> +};
> diff --git
[PATCH v2 1/3] dt-bindings: clock: meson: add A1 clock controller bindings
Add the documentation to support Amlogic A1 clock driver,
and add A1 clock controller bindings.
Signed-off-by: Jian Hu
---
.../devicetree/bindings/clock/amlogic,a1-clkc.yaml | 143 +
include/dt-bindings/clock/a1-clkc.h| 98 ++
include/dt-bindings/clock/a1-pll-clkc.h| 16 +++
3 files changed, 257 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
create mode 100644 include/dt-bindings/clock/a1-clkc.h
create mode 100644 include/dt-bindings/clock/a1-pll-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
new file mode 100644
index 000..b382eebe
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,a1-clkc.yaml
@@ -0,0 +1,143 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/clock/amlogic,a1-clkc.yaml#;
+$schema: "http://devicetree.org/meta-schemas/core.yaml#;
+
+title: Amlogic Meson A/C serials Clock Control Unit Device Tree Bindings
+
+maintainers:
+ - Neil Armstrong
+ - Jerome Brunet
+ - Jian Hu
+
+description: |+
+ The clock controller node should be the child of a syscon node with the
+ required property:
+
+ - compatible: Should be one of the following:
+"amlogic,meson-a-analog-sysctrl", "syscon",
"simple-mfd"
+"amlogic,meson-a-periphs-sysctrl", "syscon",
"simple-mfd"
+
+ Refer to the the bindings described in
+ Documentation/devicetree/bindings/mfd/syscon.txt
+
+properties:
+ "#clock-cells":
+const: 1
+ compatible:
+- enum:
+- amlogic,a1-periphs-clkc
+- amlogic,a1-pll-clkc
+
+ reg:
+maxItems: 1
+
+ clocks:
+minItems: 2
+maxItems: 6
+
+ clock-names:
+minItems: 2
+maxItems: 6
+
+required:
+ - "#clock-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+if:
+ properties:
+compatible:
+ enum:
+- amlogic,a1-periphs-clkc
+
+then:
+ properties:
+clocks:
+ minItems: 2
+ maxItems: 2
+items:
+ - description: fixed pll gate clock
+ - description: hifi pll gate clock
+
+clock-names:
+ minItems: 2
+ maxItems: 2
+ items:
+- const: xtal_fixpll
+- const: xtal_hifipll
+
+else:
+ if:
+properties:
+ compatible:
+const: amlogic,a1-pll-clkc
+
+ then:
+properties:
+ clocks:
+minItems: 6
+maxItems: 6
+items:
+ - description: Input fixed pll div2
+ - description: Input fixed pll div3
+ - description: Input fixed pll div5
+ - description: Input fixed pll div7
+ - description: Periph Hifi pll
+ - description: Input Oscillator (usually at 24MHz)
+
+ clock-names:
+minItems: 6
+maxItems: 6
+items:
+ - const: fclk_div2
+ - const: fclk_div3
+ - const: fclk_div5
+ - const: fclk_div7
+ - const: hifi_pll
+ - const: xtal
+
+
+additionalProperties: false
+
+examples:
+ - |
+analog: system-controller@0 {
+compatible = "amlogic,meson-a-analog-sysctrl",
+ "simple-mfd", "syscon";
+reg = <0 0x7c00 0 0x21c>;
+
+clkc_pll: pll-clock-controller {
+compatible = "amlogic,a1-pll-clkc";
+#clock-cells = <1>;
+clocks = <_periphs CLKID_XTAL_FIXPLL>,
+ <_periphs CLKID_XTAL_HIFIPLL>;
+clock-names = "xtal_fixpll", "xtal_hifipll";
+};
+};
+
+ - |
+periphs: system-controller@1 {
+compatible = "amlogic,meson-a-periphs-sysctrl",
+ "simple-mfd", "syscon";
+reg = <0 0x800 0 0x104>;
+
+clkc_periphs: periphs-clock-controller {
+compatible = "amlogic,a1-periphs-clkc";
+#clock-cells = <1>;
+clocks = <_pll CLKID_FCLK_DIV2>,
+<_pll CLKID_FCLK_DIV3>,
+<_pll CLKID_FCLK_DIV5>,
+<_pll CLKID_FCLK_DIV7>,
+<_pll CLKID_HIFI_PLL>,
+<>;
+clock-names = "fclk_div2", "fclk_div3", "fclk_div5",
+ "fclk_div7", "hifi_pll", "xtal";
+};
+};
diff --git a/include/dt-bindings/clock/a1-clkc.h
b/include/dt-bindings/clock/a1-clkc.h
new file mode 100644
index 000..1ba0112
--- /dev/null
+++ b/include/dt-bindings/clock/a1-clkc.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __A1_CLKC_H
+#define __A1_CLKC_H
+
+#define CLKID_XTAL_FIXPLL 1
+#define CLKID_XTAL_USB_PHY 2
+#define CLKID_XTAL_USB_CTRL3
